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參數資料
| 型號： | ADV7320 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數： | 72/88頁 |
| 文件大小： | 1002K |
| 代理商： | ADV7320 |
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ADV7320/ADV7321
The register settings in Table 41 are used to generate an SD
NTSC CVBS output on DAC A, S-video on DACs B and C, and
YPrPb on DACs D, E, and F. Upon power-up, the subcarrier
registers are programmed with the appropriate values for
NTSC. All other registers are set as normal/default.
Table 41. NTSC Test Pattern Register Writes
Subaddress
Register Setting
0x00
0xFC
0x40
0x10
0x42
0x40
0x44
0x40 (internal test pattern on)
0x4A
0x08
Rev. 0 | Page 72 of 88
For PAL CVBS output on DAC A, the same settings are used,
except that Subaddress 0x40 is programmed to 0x11 and the F
SC
registers are programmed as shown in Table 42.
Table 42. PAL F
SC
Register Writes
Subaddress
Description
0x4C
F
SC
0
0x4D
F
SC
1
0x4E
F
SC
2
0x4F
F
SC
3
Register Setting
0xCB
0x8A
0x09
0x2A
Note that when programming the F
SC
registers, the user must
write the values in the sequence F
SC
0, F
SC
1, F
SC
2, F
SC
3. The full
F
SC
value to be written is only accepted after the F
SC
3 write is
complete.
The register settings in Table 43 are used to generate a 525p
hatch pattern on DAC D, E, and F. All other registers are set as
normal/default.
Table 43. 525p Test Pattern Register Writes.
Subaddress
Ox00
0x01
0x10
0x11
0x16
0x17
0x18
Register Setting
0xFC
0x10
0x00
0x05
0xA0
0x80
0x80
For 625p hatch pattern on DAC D, the same register settings are
used except that Subaddress 0x10 = 0x18.
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