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參數(shù)資料
型號: ADV7320
廠商: Analog Devices, Inc.
英文描述: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
中文描述: 多格式視頻編碼器216兆赫六噪聲整形的12位DAC
文件頁數(shù): 46/88頁
文件大小: 1002K
代理商: ADV7320
ADV7320/ADV7321
VERTICAL BLANKING INTERVAL
The ADV7320/ADV7321 accepts input data that contains VBI
data (such as CGMS, WSS, VITS) in SD and HD modes.
Rev. 0 | Page 46 of 88
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Lines 13 to 42 of each frame, or on Lines 6 to 43 for
the ITU-R BT.1358 (625p) standard.
This data can be present on Lines 10 to 20 for SD NTSC and on
Lines 7 to 22 for PAL.
If VBI is disabled [Address 0x11, Bit 4 for HD; Address 0x43,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.
In Slave Mode 0, if VBI is enabled, the blanking bit in the
EAV/SAV code is overwritten. It is possible to use VBI in this
timing mode as well.
In Slave Mode 1 or 2, the BLANK control bit must be enabled
[Address 0x4A, Bit 3] to allow VBI data to pass through the
ADV7320/ADV7321. Otherwise, the ADV7320/ADV7321
automatically blanks the VBI to standard.
If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.
See Appendix 1—Copy Generation Management System.
SUBCARRIER FREQUENCY REGISTERS
[Subaddresses 0x4C to 0x4F]
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the equation
32
2
27
×
=
in
line
video
one
in
cycles
clk
MHz
of
Number
line
video
one
periods
subcarrier
of
Number
Register
Frequency
Subcarrier
where the sum is rounded to the nearest integer.
For example, in NTSC mode
569408543
1716
5
227
2
32
=
×
=
Value
Register
Subcarrier
where:
Subcarrier Register Value
= 0x21F07C1F
SD F
SC
Register 0: 0x1F
SD F
SC
Register 1: 0x7C
SD F
SC
Register 2: 0xF0
SD F
SC
Register 3: 0x21
See the MPU Port Description section for more details on
accessing the subcarrier frequency registers.
Programming the F
SC
The subcarrier register value is divided into 4 F
SC
registers as
shown above. To load the value into the encoder, users must
write to the F
SC
registers in sequence, starting with F
SC
0. The
value is not loaded until the F
SC
4 write is complete.
Note that the ADV7320/ADV7321 power-up value for F
SC
0 is
0x1E. For precise NTSC F
SC
, write 0x1F to this register.
相關(guān)PDF資料
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