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參數(shù)資料
| 型號(hào)： | ADV7344BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| 中文描述： | SERIAL INPUT LOADING, 14-BIT DAC, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁(yè)數(shù)： | 15/88頁(yè) |
| 文件大小： | 1078K |
| 代理商： | ADV7344BSTZ |
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ADV7344
Rev. 0 | Page 15 of 88
Y0
Y1
Y2
Y3
b
a
Cr2
Cb2
Cr0
Cb0
c
Y OUTPUT
Y9 TO Y2/Y9 TO Y0
C9 TO C2/C9 TO C0
P_HSYNC
P_VSYNC
P_BLANK
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 16. HD-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
0
Y9 TO Y2/Y9 TO Y0
Cb0
Y0
Cr0
Y1
b
a
P_HSYNC
P_VSYNC
P_BLANK
c
Y OUTPUT
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
0
Figure 17. HD-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
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