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參數(shù)資料
| 型號： | ADV7344BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| 中文描述： | SERIAL INPUT LOADING, 14-BIT DAC, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 74/88頁 |
| 文件大小： | 1078K |
| 代理商： | ADV7344BSTZ |
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ADV7344
APPENDIX 4—INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV7344 is able to generate SD color bar and black bar
test patterns.
The register settings in Table 56 are used to generate an SD
NTSC 75% color bar test pattern. CVBS output is available on
DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and
YPrPb output is on DAC 1 to DAC 3. Upon power-up, the
subcarrier frequency registers default to the appropriate values
for NTSC. All other registers are set as normal/default.
Rev. 0 | Page 74 of 88
Table 56. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
0x00
0x82
0x84
Setting
0xFC
0xC9
0x40
To generate an SD NTSC black bar test pattern, the same
settings shown in Table 56 should be used with an additional
write of 0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used,
except that Subaddress 0x80 is programmed to 0x11 and the
subcarrier frequency registers are programmed as shown in
Table 57.
Table 57. PAL F
SC
Register Writes
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
F
SC
0
F
SC
1
F
SC
2
F
SC
3
Setting
0xCB
0x8A
0x09
0x2A
Note that when programming the F
SC
registers, the user must
write the values in the sequence F
SC
0, F
SC
1, F
SC
2, F
SC
3. The full
F
SC
value to be written is accepted only after the F
SC
3 write is
complete.
ED/HD TEST PATTERNS
The ADV7344 is able to generate ED/HD color bar, black bar,
and hatch test patterns.
The register settings in Table 58 are used to generate an ED
525p hatch test pattern. YPrPb output is available on DAC 1 to
DAC 3. All other registers are set as normal/default.
Table 58. ED 525p Hatch Test Pattern Register Writes
Subaddress
0x00
0x01
0x31
Setting
0x1C
0x10
0x05
To generate an ED 525p black bar test pattern, the same settings
as shown in Table 58 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the same settings
shown in Table 58 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the same settings as
shown in Table 58 (and subsequent comments) are used except
that Subaddress 0x30, Bits[7:3] are updated as appropriate.
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