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參數資料
| 型號： | ADV7393EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標清/高清視頻編碼器 |
| 文件頁數： | 12/96頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | ADV7393EBZ |
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ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 12 of 96
Y0
Y1
Y2
Y3
a
Cr2
Cb2
Cr0
Cb0
b
Y OUTPUT
HSYNC
VSYNC
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
PIXEL PORT*
0
Figure 10. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Cb0
Y0
Cr0
Y1
a
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 11. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
HSYNC
VSYNC
b
Y OUTPUT
PIXEL PORT
0
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PDF描述 |
|---|---|
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| ADV7400ABSTZ-1101 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400AKSTZ-110 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400AKSTZ-1101 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7393WBCPZ | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays |
| ADV7393WBCPZ-REEL | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel |
| ADV73946603 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73946604 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73946902 | 制造商:LG Corporation 功能描述:Frame Assembly |
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