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參數資料
| 型號： | ADV7393EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標清/高清視頻編碼器 |
| 文件頁數： | 43/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7393EBZ |
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ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 upon either the rising or falling
edge of CLKIN. P8/P6 is the LSB.
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
upon the opposite edge of CLKIN. P8/P6 is the LSB.
10-bit mode is enabled using Subaddress 0x33, Bit 2. Whether
the Y data is clocked in upon the rising or falling edge of CLKIN
is determined by Subaddress 0x01, Bits[2:1] (see Figure 55 and
Figure 56).
Rev. 0 | Page 43 of 96
3FF
00
00
X
Y
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
P[15:8]/
P]15:6]
Cb0
0
Figure 55. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
3FF
00
00
XY
Cb0
Cr0
Y1
CLKIN
P[15:8]/
P[15:P6]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
Figure 56. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
0
M
PEG2
DECODER
CLKIN
P[7:0]
P[15:8]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8
CrCb
8
Y
2
0
Figure 57. ED/HD-SDR Example Application
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8/10
2
YCrCb
0
Figure 58. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with P8/P6 being the LSB.
10-bit mode is enabled using Subaddress 0x33, Bit 2.
3FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
P[15:8]/P[15:6]
NOTES
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
0
Figure 59. ED (At 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
54MHz
ADV7392/
ADV7393
VSYNC,
HSYNC
YCrCb
8/10
YCrCb
2
INTERLACED TO
PROGRESSIVE
0
Figure 60. ED (At 54 MHz) Example Application
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7393WBCPZ | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays |
| ADV7393WBCPZ-REEL | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel |
| ADV73946603 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73946604 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73946902 | 制造商:LG Corporation 功能描述:Frame Assembly |
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