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參數資料
型號： ADV7393EBZ
廠商： Analog Devices, Inc.
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： 低功耗，芯片尺寸10位標清/高清視頻編碼器
文件頁數： 91/96頁
文件大小： 1209K
代理商： ADV7393EBZ
ADV7390/ADV7391/ADV7392/ADV7393
Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Rev. 0 | Page 91 of 96
Table 97. 16-Bit 625p YCrCb In, RGB Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x10
0x02
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x30
0x18
0x31
0x01
Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
相關PDF資料
PDF描述
ADV7400AKSTZ-80 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400AKSTZ-801 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400ABSTZ-1101 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400AKSTZ-110 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
ADV7400AKSTZ-1101 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
相關代理商/技術參數
參數描述
ADV7393WBCPZ 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays
ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
ADV73946604 制造商:LG Corporation 功能描述:Frame Assembly
ADV73946902 制造商:LG Corporation 功能描述:Frame Assembly
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