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| 型號： | ADV7393EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器 |
| 文件頁數(shù)： | 71/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7393EBZ |
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ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 4–INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV739x is able to generate SD color bar and black bar
test patterns.
The register settings in Table 55 are used to generate an SD NTSC
75% color bar test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. Upon power-up, the subcarrier frequency registers
default to the appropriate values for NTSC.
Rev. 0 | Page 71 of 96
Table 55. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
0x00
0x82
0x84
Setting
0x1C
0xC9
0x40
For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9
should be written to Subaddress 0x82.
For component RGB output rather than YPrPb output, 0 should
be written to Subaddress 0x02, Bit 5.
To generate an SD NTSC black bar test pattern, the same
settings shown in Table 55 should be used with an additional
write of 0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used,
except that Subaddress 0x80 is programmed to 0x11 and the
subcarrier frequency (F
SC
) registers are programmed as shown
in Table 56.
Table 56. PAL F
SC
Register Writes
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
F
SC
0
F
SC
1
F
SC
2
F
SC
3
Setting
0xCB
0x8A
0x09
0x2A
Note that when programming the F
SC
registers, the user must
write the values in the sequence F
SC
0, F
SC
1, F
SC
2, F
SC
3. The full
F
SC
value to be written is only accepted after the F
SC
3 write is
complete.
ED/HD TEST PATTERNS
The ADV739x is able to generate ED/HD color bar, black bar,
and hatch test patterns.
The register settings in Table 57 are used to generate an ED
525p hatch test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. For component RGB output rather than YPrPb output,
0 should be written to Subaddress 0x02, Bit 5.
Table 57. ED 525p Hatch Test Pattern Register Writes
Subaddress
0x00
0x01
0x31
Setting
0x1C
0x10
0x05
To generate an ED 525p black bar test pattern, the same settings
as shown in Table 57 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the same settings
shown in Table 57 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the same settings as
shown in Table 57 (and subsequent comments) are used except
that Subaddress 0x30, Bits[7:3] are updated as appropriate.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| ADV73946902 | 制造商:LG Corporation 功能描述:Frame Assembly |
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