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參數資料
型號: ISP1501
英文描述: Hi-Speed Universal Serial Bus peripheral transceiver
中文描述: 高速通用串行總線外設收發器
文件頁數: 16/40頁
文件大小: 770K
代理商: ISP1501
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
16 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
10.2 High-speed receive
When ISP1501 is in high-speed state (MODE[1:0] = 02H), setting input DDIR to
logic 0 allows the HS receiver to output data to the external 16-bit bus. As the length
of the incoming EOP is not fixed, RX_LAST_BYTE and RX_BS_ERROR are
encoded to differentiate between EOP arriving on an 8-bit or a 16-bit boundary.
RX_VALID qualifies the data part of USB high-speed traffic. The SYNC pattern bytes
are removed.
If the EOP arrives on the high byte, RX_VALID will qualify it, and RX_LAST_BYTE
will be asserted. With these, the SIE will know that an EOP has occurred and can
start deciphering the received packet.
If the EOP arrives on the low byte, RX_VALID goes LOW at the start of the EOP
cycle. RX_BS_ERROR must be polled to determine whether an EOP has occurred.
(1) TX_READY is only de-asserted during a transmission if the internal FIFO is full.
Fig 11. HS transmit; 5-byte EOP ending on 8-bit boundary.
MGT069
00H
SYNC
80H
Data0(H)
Data1(H)
Data2(H)
Data3(H)
Data4(H)
FFH
FFH
XX
00H
00H
Data0(L)
Data1(L)
Data2(L)
Data3(L)
Data4(L)
FEH
FFH
FFH
CLKOUT30
DATA[7:0]
DATA[15:8]
TX_READY
TX_LAST_BYTE
TX_BS_EN
TX_VALID
EOP
(1)
(1) TX_READY is only de-asserted during a transmission if the internal FIFO is full.
Fig 12. HS transmit; 5-byte EOP ending on 16-bit boundary
MGT065
00H
SYNC
80H
Data0(H)
Data1(H)
Data2(H)
Data3(H)
Data4(H)
FEH
FFH
FFH
00H
00H
Data0(L)
Data1(L)
Data2(L)
Data3(L)
Data4(L)
Data5(L)
FFH
FFH
CLKOUT30
DATA[7:0]
DATA[15:8]
TX_READY
TX_LAST_BYTE
TX_BS_EN
TX_VALID
EOP
(1)
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