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參數(shù)資料
型號(hào): ISP1501
英文描述: Hi-Speed Universal Serial Bus peripheral transceiver
中文描述: 高速通用串行總線外設(shè)收發(fā)器
文件頁(yè)數(shù): 21/40頁(yè)
文件大小: 770K
代理商: ISP1501
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
21 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11. Clocking
The CLKOUT30 and CLKOUT48 pins are free running clocks at 30 MHz and 48 MHz,
respectively.
11.1 Power-up behavior
Both output clocks (CLKOUT30 and CLKOUT48) are held LOW (logic 0) at power-up
for a period of up to 8192 oscillator cycles before they are enabled.
The time during which these output clocks are blocked depends on the start-up time
of the external crystal. A total of 8192 oscillator clock ticks must be counted before
enabling the output clocks. Therefore, the minimum timing from power-up to the time
when CLKOUT30 and CLKOUT48 are available is 8192 x 83 ns = 680
μ
s.
11.2 Suspend behavior
When SUSPEND is driven from logic 0 to logic 1, output clocks will stop toggling
because the internal PLL and the external crystal will also enter a power-down state.
The clocks CLKOUT30 and CLKOUT48 can stop at either logic 0 or logic 1.
When SUSPEND is driven from logic 1 to logic 0, the external crystal and the PLL will
start again. However, there is no blocking of output clocks. CLKOUT30 and
CLKOUT48 may drift slightly from 30 MHz and 48 MHz, respectively until the PLL
locks up.
11.3 Reset behavior
A pin reset will force the digital circuit that generates 30 MHz and 48 MHz from the
HS PLL (480 MHz) to the initial state. Therefore, the output clock at 30 MHz and
48 MHz will be aligned after pin RESET is driven from logic 1 to logic 0 (falling edge).
During that one instance, the alignment causes the clock period to change.
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