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參數(shù)資料
| 型號： | ISP1501 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral transceiver |
| 中文描述： | 高速通用串行總線外設(shè)收發(fā)器 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大小： | 770K |
| 代理商： | ISP1501 |
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Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
8 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
intended states without slew-rate control. This is permitted because driving during
suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from
idle to the ‘K’ state) for a period of 1 to 15 ms.
7.2 High-speed (HS) transceiver—transmit logic
The high-speed (HS) transceiver interface uses a 16-bit parallel bi-directional data
interface. This HS module incorporates bit stuffing/de-stuffing and
Non-Return-to-Zero-Inverted (NRZI) encoding/decoding logic. Access to the HS
interface requires MODE[1:0] to be set to either the high-speed (HS) state or the
high-speed (HS) chirp state.
When MODE[1:0] pins are in the HS or HS chirp states, the HS transceiver is active
and follows the protocol as specified in
Section 10.1
,
Section 10.2
and
Section 10.3
.
One difference between the HS and HS chirp states is that the RPU resistor is
disconnected when MODE[1:0] is in the HS state whereas the RPU resistor is
connected to the DP line when MODE[1:0] is in the HS chirp state. Another difference
between the HS and HS chirp state is that the 45
terminations are disabled from
the DP and DM lines in the HS chirp state.
The 16-bit data bus is a bi-directional bus. Pin DDIR must be set to logic 1 for
clocking data into the 16-bit DATA[15:0] bus so that the payload is transmitted from
the device to the host. If pin DDIR is set to logic 0, the 16-bit data bus is an output to
the external ASIC. Any payload transferred from the host/hub to the transceiver is
clocked out into the 16-bit data bus.
The transmit data is clocked on the rising edge of the 30 MHz clock output
(CLKOUT30). All the handshake signals (TX_LAST_BYTE, TX_BS_EN and
TX_VALID) are latched at the same time. These signals conform to the same set-up
and hold times as specified in
Section 17.1
. Each set of latched data, including the
16-bit data bus and handshake signals, are qualified if TX_VALID and TX_READY
are asserted during latching. TX_READY transitions take place on the falling edge of
the 30 MHz clock output.
For normal HS transmit, TEST_J_K is set to logic 0. The HS logic will process the
16-bit data with the latched TX_LAST_BYTE and TX_BS_EN signals according to
Table 7
, and the processed data is serially driven on the USB bus in HS signaling.
When TEST_J_K is set to logic 1, the TX_BS_EN signal is ignored. The 16-bit input
data will be serially driven on the bus in HS signaling with the NRZI and bit-stuffing
disabled.
7.3 High-speed (HS) transceiver—receive logic
For receiving high-speed (HS) USB signals, the incoming differential signal from the
USB cable is amplified before it is fed into a sampler circuit. In the normal receive
mode, TEST_J_K is set to logic 0 and the over-sampled serial data is NRZI decoded
and bit de-stuffed before being converted to 16-bit parallel words. The 16-bit data and
other handshake signals (RX_BS_ERROR, RX_LAST_BYTE and RX_VALID) are
latched on the falling edge of CLKOUT30 in accordance with the timings as specified
in
Table 18
.
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| ISP1504A1_07 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver |
| ISP1504A1ET | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver |
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