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參數(shù)資料
| 型號(hào)： | L64020XDC |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MINI, BGA-208 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大小： | 370K |
| 代理商： | L64020XDC |
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18
L64020 Single Chip DVD Decoder
LRCLK
DAC Left/Right Sample Clock
Output
Used to indicate which samples belong to the left and right
stereo channels. In default mode, LRCLK is set HIGH
when the right channel sample is on the ASDATA pin and
cleared to LOW when the left channel sample is on the
ASDATA pin. The host can invert the sense of the clock
(HIGH for left channel, LOW for right).
A_ACLK
DAC Clock
Output
This clock is buffered from the selected input ACLK_x
(see the following ACLK_x description). In CD-bypass
mode, this clock comes directly from the CD_ACLK input
pin.
AUDIO_SYNCn
Audio Sync Strobe
Output
Provides an indication of Audio Decoder synchronization
to the bitstream. Use in transport systems requiring
hardware sync controls. This is an active LOW pulse at
the time of the audio frame decode start.
ACLK_32, ACLK_441, ACLK_48
Audio Reference Clocks
Input
Host selectable audio reference clocks from which clocks
for the external DAC, internal DAC Interface, and internal
S/P DIF Interface are derived.
ACLK_32 = 32 kHz x N,
ACLK_441 = 44.1 kHz x N, and
ACLK_48 = 48 kHz x N
where N = 768, 384, 512, or 256.
At least one of the three ACLK_ inputs must be supplied
and it must be integrally divisible into the required sample
rate clocks. The host selects the input clock and the
divisor.
SPDIF_IN
External S/P DIF
Input
This input is directly connected to the SPDIF_OUT pin
when the host selects the S/P DIF Bypass mode.
SPDIF_OUT
S/P DIF Output
Output
IEC958 formatted output of the L64020’s S/P DIF
Interface in normal modes and SPDIF_IN in S/P DIF
Bypass mode.
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