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參數資料
| 型號： | L64020XDC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MINI, BGA-208 |
| 文件頁數： | 11/32頁 |
| 文件大小： | 370K |
| 代理商： | L64020XDC |
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L64020 Single Chip DVD Decoder
19
Miscellaneous and Test Interfaces
PLLVDD
PLL Power Supply
Input
This pin provides power (3.3 V) to the on-chip PLL for
deriving the 81 MHz SDRAM clock.
PLLVSS
PLL Ground
Input
This pin provides ground to the on-chip PLL for deriving
the 81 MHz SDRAM clock.
RESETn
Reset
Input
When RESETn is asserted, the L64020 resets its internal
microcontroller, FIFO controllers, state machines, and
registers.
SYSCLK
Device Clock
Input
Device clock has a nominal frequency of 27 MHz. Picture
reconstruction and video timing are referenced with
respect to this clock. SYSCLK also drives the PLL to
generate the 81 MHz clock for the SDRAM interface.
TM[1:0]
Test Mode
Input
These inputs are used by LSI Logic during manufacturing
test. They are not exercised in a customer system. They
should both be tied to VSS in the system.
ZTEST
Test Mode
Input
Test mode pin. This should be tied to VDD in the system
for normal operation.
SCAN_TE
Test Mode
Input
Test mode pin. This should be tied to VSS in the system
for normal operation.
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