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參數資料
| 型號： | L64020XDC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MINI, BGA-208 |
| 文件頁數： | 9/32頁 |
| 文件大?。?/td> | 370K |
| 代理商： | L64020XDC |
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L64020 Single Chip DVD Decoder
17
VS
Vertical Sync/Odd-Even Field Indicator
Input
VS is the vertical sync signal from the PAL/NTSC
Encoder. It can be programmed to be either a
conventional vertical sync input or an even/odd eld
indicator. In the even/odd eld indicator mode, the
internal display controller counters reset each time VS
changes state (at the beginning of each eld). The
polarity of the eld is controlled by the timing of VS
relative to HS. VS should be synchronous to SYSCLK.
Audio Interface
CD_ASDATA
CD Mode Audio Data
Input
Unencoded serial audio data from a CD or other storage
device. Connected directly to the ASDATA output when
the host selects the CD Bypass mode.
CD_BCLK
CD Mode DAC Bit Clock
Input
Bit clock from CD player. Connected directly to the BCLK
output when the host selects the CD Bypass mode.
CD_LRCLK
CD Mode DAC Left/Right Clock
Input
Left/right sample clock from CD player. Connected
directly to the LRCLK output when the host selects the
CD Bypass mode.
CD_ACLK
CD Mode DAC Clock
Input
DAC clock from CD player. Connected directly to the
A_ACLK output when the host selects the CD Bypass
mode.
ASDATA
Audio Serial Data
Output
Serial audio data from the L64020’s Audio Decoder in
nonbypass modes. The data can be Dolby Digital,
MPEG, or Linear PCM audio. Serial audio data from the
CD_ASDATA input in CD Bypass mode.
BCLK
DAC Bit Clock
Output
Serial data bit clock used by the L64020’s DAC Interface
to serialize the decoded audio data and by the external
DAC to clock it in on the rising edge. BCLK is derived
from one of the ACLK_x inputs under host control in
normal modes and is the CD_BCLK input in CD Bypass
mode.
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