- 您現在的位置：買賣IC網 > PDF目錄30712 > L64020XDC (LSI CORP) SPECIALTY CONSUMER CIRCUIT, CBGA208 PDF資料下載
參數資料
| 型號： | L64020XDC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MINI, BGA-208 |
| 文件頁數： | 5/32頁 |
| 文件大小： | 370K |
| 代理商： | L64020XDC |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
L64020 Single Chip DVD Decoder
13
INTRn
Interrupt
OD Output
INTRn is an active LOW, open-drain, output signal. The
L64020 asserts this signal to alert the host that an
unmasked interrupt condition has occurred in the chip.
DREQn
DMA Transfer Request
Output
The L64020 asserts this signal when it is ready to receive
a new byte of data from or transmit a new byte of data to
an external DMA controller. The state of DREQn reects
the condition of internal read and write FIFOs. For DMA
write cycles, DREQn is deasserted when the write FIFO
is not near full (more than one space left) and deasserted
when the FIFO is near full. For read cycles, DREQn is
asserted when the read FIFO is not near empty (more
than one space lled) and deasserted when the FIFO is
near empty. The maximum transfer rate over this
interface is 20 Mbits/s in worst case conditions. The peak
data rate may increase above this depending on system
SDRAM usage.
PREQn
PCM FIFO Request
Output
The L64020 asserts this signal when it is ready to receive
a new byte of data in the PCM FIFO, i.e., when the FIFO
is not near full (less than 25 bytes unread). The PCM
FIFO allows the host to send Linear PCM audio samples
to the Audio Decoder in the L64020. PREQn can be used
as a request signal to an external DMA controller.
Channel Interface
AREQn
Audio Transfer Request
Output
The L64020 asserts AREQn when it is ready to receive
a new byte of coded audio data in A/V PES stream mode
(from a transport stream demultiplexer) or a new byte of
any data in program stream modes. The decoder is ready
when the channel input FIFO is not near full.
VREQn
Video Transfer Request
Output
The L64020 asserts VREQn when it is ready to receive
a new byte of coded audio data in A/V PES stream mode
(from a transport stream demultiplexer). The decoder is
ready when the channel input FIFO is not near full.
VREQn is not used in program stream modes.
相關PDF資料 |
PDF描述 |
|---|---|
| L64020XQC | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| L64020XBC | SPECIALTY CONSUMER CIRCUIT, PQFP176 |
| L64021HG | SPECIALTY CONSUMER CIRCUIT, PBGA208 |
| L64021MS | SPECIALTY CONSUMER CIRCUIT, PQFP176 |
| L64021PZ | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| L6402MH10RI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:128 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O⑩ Control |
| L6402ML11RI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:128 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O⑩ Control |
| L64032AGC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| L64032AGCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| L64032AGM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
發布緊急采購，3分鐘左右您將得到回復。