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參數資料
| 型號： | L64020XDC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, MINI, BGA-208 |
| 文件頁數： | 4/32頁 |
| 文件大?。?/td> | 370K |
| 代理商： | L64020XDC |
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12
L64020 Single Chip DVD Decoder
WRITEn - Intel Mode
The external host asserts WRITEn to start a write cycle.
READn must be HIGH during a write cycle, and CSn
must be LOW during a write cycle. The address is
registered on the falling edge of WRITEn. The data is
latched by the L64020 on the rising edge of WRITEn.
READ/READn Read/Write Indicator/Read Strobe
Input
READ - Motorola Mode
The Motorola host sets READ HIGH for a read cycle and
clears it LOW for a write cycle. CSn must be asserted to
select the L64020.
READn - Intel Mode
The Intel host asserts READn and holds WRITEn
deasserted to perform a read cycle. The address is
registered on the falling edge of READn. CSn must be
asserted to select the L64020.
DTACKn/RDYn
Data Acknowledge/Data Ready
3-State Output
DTACKn - Motorola Mode
The L64020 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. DTACKn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64020 deasserts
DTACKn before the cycle is completed.
RDYn - Intel Mode
The L64020 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. RDYn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64020 deasserts
RDYn before the cycle is completed.
WAITn
Wait
3-State Output
This signal may be used instead of DTACKn/RDYn by
hosts that require an inverted sense. The L64020 asserts
WAITn to indicate that its Host Interface is busy with a
read or write bus cycle and it deasserts it when the
current cycle is completed. WAITn is 3-stated when CSn
is not active.
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