
LC6512A, LC6513A
No.2367–11/24
(1) Ports A
0
to 3, B
0
to 3
Functions 4-bit input (IP instruction)
Single-bit test (BP, BNP instructions)
Port A: Low-threshold input
Port B: Normal-threshold input
(2) Ports C
0
to 3, D
0
to 3
Functions 1. Input mode (Output inhibit)
4-bit input (IP instruction)
Single-bit test (BP, BNP instructions)
2. Output mode
4-bit output (OP instruction)
Single-bit set, reset (SPB, RPB instructions)
(3) Ports E
0
to 3, F
0
to 3, G
0
to 3, H
0
to 3, I
0
to 1 (High-voltage ports)
Functions 4-bit (2-bit for port I) output (OP instruction)
4-bit (2-bit for port I) input of output latch contents (IP instruction)
Single-bit set, reset (SPB, RPB instructions)
Set: The output represents a 1. ----- Output transistor ON
Reset: The output represents a 0. ----- Output transistor OFF
Single-bit test of output latch contents (BP, BNP instructions)
PortsE, F, I: FLT digits drive
Ports G, H: FLT segments drive
Internal bus
Ports A,B
DSB
---
Input inhibit at HOLD mode
Internal bus
DSB
---
Output control (Control register)
Ports C,D
Internal bus
Ports E to I
DSB
=
Output inhibit at HOLD mode (Output transistor OFF)
DSB
---
Input output inhibit at HOLD mode
Output: High impedance
Output
inhibit