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參數資料
| 型號： | LA6513A |
| 文件頁數： | 14/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | LA6513A |
LC6512A, LC6513A
No.2367–14/24
Appendix 4. Standby Function
Two standby modes – HALT mode and HOLD mode – are available to minimize the power dissipation when the program
is in the wait state or a power failure is backed up. Both modes are set with the execution of the HALT instruction. All the
operations including the system clock generator are stopped at the standby mode. (For other models LC6502/05 of the
LC6500 series, the HOLD mode is hardware-set with the HOLD pin = "L". Be careful of the difference in the mode setting
method.)
The HALT mode and HOLD mode are used properly depending on the purposes. They are different in the mode setting
conditions, I/O port state during standby operation, mode releasing method. The HALT mode is entered by executing the
HALT instruction when the HOLD pin is at H-Level. The HALT mode is used to save the power dissipation when the
program is in the wait state. The HOLD mode is entered by executing the HALT instruction when the HOLD pin is at L-
Level. At the HOLD mode all I/O ports are disabled and there is no power dissipation in the interfaces with external
circuits, permitting capacitor or battery-used power supply backup during power failure.
4-1. HALT mode setting
The HALT mode is entered by executing the HALT instruction when the HOLD pin is at H-Level and all pins for port
A
0
to A
3
are at L-Level. When even one of pins for port A
0
to A
3
is at H-Level, the HALT instruction is disregarded
and becomes equal to the NOP instruction.
The HALT mode causes individual blocks to be placed in the following states.
(1)
All the operations including the system clock generator are stopped.
(2)
The state immediately before setting the HALT mode is held.
(3)
Timer............State where all bits are set to "1"(max.time).
Status flag.....The EXTF, TMF are reset (interrupt disable). The CF, ZF contents are held. An interrupt request at the
HALT mode is disregarded.
(4)
For the registers, data RAM, port output latch, PC (except those in (3), the contents immediately before setting the
HALT mode are held.
4-2. HOLD mode setting
The HOLD mode is entered by executing the HALT instruction when the HOLD pin is at L-Level. ln this case, the
contents of port A
0
to A
3
remain unaffected.
The state in the HOLD mode is the same as that in the HALT mode, except the state of I/O port. The HOLD mode
permits the undermentioned power-down mode to be entered.
lnput ports A, B: lnput inhibit
Input/output port C, D: Input inhibit, output high impedance
Output ports E to I: Output Pch transistor OFF
INT, RES pins: Input inhibit
For the output latch of the output port, the contents immediately before setting the HOLD mode are held.
I/O port
Operation is stopped
I/O port
Blocks to be cleared/reset
Blocks to be held
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