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參數資料
| 型號： | LA6513A |
| 文件頁數： | 21/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | LA6513A |
LC6512A, LC6513A
No.2367–21/24
If the ZF is 0, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
If a fiag bit of the 16 flags specified by
immediate data n3n2n1n0 is 1,a branch to
an address specified by immediate data P7
to P0 within the current page occurs.
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If ZF=0
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If Fn=1
AC
←
[P(DPL)]
If the ZF is 1, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If Fn=0
If the EXTF is 1, a branch to an
address specified by immediate data
P7 to P0 within the current page
occurs. The EXTF is reset.
If the EXTF is 0, a brance to an
address specified by immediate data
P7 to P0 within the current page
occurs. The EXTF is reset.
If the CF is 1, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
If the CF is 0, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
P(DPL)
←
(AC)
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If EXTF=1
then EXTF
←
0
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If EXTF=0
then EXTF
←
0
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If CF=1
0 0 1 0
1 0 0 0
1 1 0 0
B
3B2B1B0
0 0 1 0
1 0 0 1
0 0 1 0
0 0 0 0
2
P(DPL B1B0)
←
0
CTL
←
(CTL)
B3B2B1B0
CTL
←
(CTL)
B3B2B1B0
0 1 1 0
2
P(DPL B1B0)
←
1
Set control register
bit(S)
Reset port bit
Reset control register
bit(S)
Output AC to port
Write timer
Set port bit
1 1 1 1
Input port to AC
1
TM
←
(E).(AC)
TMF
←
0
Halt
2
1
1 0 0 1
0 1 1 1
P7P6P5P4
Branch on interrupt
1 1 0 1
P3P2P1P0
2
Branch on no flag bit
Branch on no lnterrupt
Branch on no ZF
Branch on CF
Branch on flag bit
Branch on ZF
Branch on no CF
0 1 1 1
P7P6P5P4
1 1 1 0
P3P2P1P0
n3n2n1n0
P3P2P1P0
n3n2n1n0
P3P2P1P0
2
1 1 1 1
P3P2P1P0
1 1 1 1
P3P2P1P0
1 1 1 0
P3P2P1P0
0 1 B1B0
1 1 0 0
B
3B2B1B0
1 1 0 0
2
0 0 0 1
0 1 B1B0
1
1
2
1
2
1
2
2
2
2
2
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If ZF=1
0 0 1 1
P7P6P5P4
1 1 0 1
P3P2P1P0
The E and AC contents are loaded in
the timer. The TMF reset.
All operations stop.
2
2
1 1 0 1
P7P6P5P4
0 0 1 l
P7P6P5P4
1 0 0 1
P7P6P5P4
0 0 l l
P7P6P5P4
0 1 1 l
P7P6P5P4
2
1
2
1
2
2
0 0 0 0
2
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If CF=0
2
2
BNTM
addr
Mnemonic
TMF
Remarks
Status
flag
affected
Description
B
Instruction code
Function
C
ZF
ZF
ZF
Mnemonic is
BFO to BF15
according to
the value of n.
Mnemonic is
BNFO to
BNF15
according to
the value of n.
No operation is performed, but 1
machine cycle is consumed.
When this instruct-
E register contents
are destroyed.
Immediate data B3B2B1B0-specified
bits in the control register are reset.
B
I
O
NOP
I
No operation
1
1
0 0 0 0
0 0 0 0
No operation
Mnemonic is
BNFO to BNF15
according to the
value of n.
If the TMF is 0, a branch to an
address specified by immediate data
P7 to P0 within the current page
occurs. The TMF is reset.
TMF
PC7 to 0
←
P7P6P5P4
P3P2P1P0
If TMF=0
then TMF
←
0
EXTF
2
EXTF
0 0 1 1
P7P6P5P4
D7D6D5D4
2
1 1 0 0
P3P2P1P0
D3D2D1D0
The AC contents are outputted to port
P(DPL)
Immediate data B1B0- specified one
bit in port p(DPL)is set.
The contents of port P(DPL) are inputted to
Immediate data B3B2B1B0-specified
bits in the control register are set.
If a fiag bit of the 16 flags specified by
immediate data n3n2n1n0 is 1,a branch to
an address specified by immediate data P7
to P0 within the current page occurs.
Branch on no timer
Immediate data B1B0- specified one
bit in port p(DPL)is reset.
HALT
1 1 1 1
Halt
WTTM
RCTL
bit
0 1 1 0
SCTL
bit
1
1
IP
BZ addr
BNC
addr
BNI
addr
RPB bit
BC addr
BNZ
addr
SPB bit
OP
BI addr
BNFn
addr
BFn
addr
*1 lf the LI instruction or CLA instruction is used consecutively in such a manner as LI, LI, LI……,or CLA,
CLA, CLA, ……, the first LI instruction or CLA instruction only is effective and the following LI in-
structions or CLA instructions are changed to the NOP instructions.
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