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參數(shù)資料
| 型號(hào)： | LA6513A |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大?。?/td> | 332K |
| 代理商： | LA6513A |
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LC6512A, LC6513A
No.2367–4/24
Continued from preceding page.
Function
Input
Input/Output
Input port B0 to B3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch
PC0-3
PE0-3
PD0-3
Pin Name
Input/Output
PB0-3
Output
Output
Input/Output
Input
Input
Output
Output
PF0-3
Output
Output
Output port I0, I1 (Digit driver output)
Capable of 2-bit output and single-bit set/reset
Capable of 2-bit input of output latch contents and single-bit decision of output latch for branch
A ceramic resonator is connected to this pin and pin OSC2 in the internal clock mode.
Output port H0 to H3 (Segment driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Output port G0 to G3 (Segment driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Connected to 0V power supply
Power supply pin
Normally connected to +5V
Pin for externally connecting a resonance circuit for the internal clock mode
Input/output common port C0 to C3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch during input
Capable of 4-bit output and single-bit set/reset during output
Input/output common port D0 to D3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch during input
Capable of 4-bit output and single-bit set/reset during output
Output port F0 to F3 (Digit driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Output port E0 to E3 (Digit driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
0SC2
PG0-3
0SC1
IC test pin
Normally connected to VSS(0V)
PH0-3
Pl0, 1
Input
VDD
TEST
VSS
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S
(Note1) For pin OSCl, up to oscillation amplitude generated when internally oscillated under the recommended
oscillation conditions in Fig. 2 is allowable.
[Note] When mounting the QIP package version on the board, do not dip it in solder.
O
o
0
o
5
3
–
5
e
g
+
–
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
=0V
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