
Communications Processor (CP)
4-20
MC68302 USER’S MANUAL
MOTOROLA
NMSI mode. The SIMODE register is a memory-mapped read-write register cleared by re-
set.
SETZ—Set L1TXD to zero (valid only for the GCI interface)
0 = Normal operation
1 = L1TXD output set to a logic zero (used in GCI activation, refer to 4.4.2 GCI Inter-
face)
SYNC/SCIT—SYNC Mode/SCIT Select Support
SYNC is valid only in PCM mode.
0 = One pulse wide prior to the 8-bit data
1 = N pulses wide and envelopes the N-bit data
The SCIT (Special Circuit Interface T) interface mode is valid only in GCI mode.
0 = SCIT support disabled
1 = SCIT D-channel collision enabled. Bit 4 of channel 2 C/I used by the IMP for receiv-
ing indication on the availability of the S interface D channel.
SDIAG1–SDIAG0—Serial Interface Diagnostic Mode (NMSI1 Pins Only)
00 = Normal operation
01 = Automatic echo
The channel automatically retransmits the received data on a bit-by-bit basis. The
receiver operates normally, but the transmitter can only retransmit received data.
In this mode, L1GR is ignored.
10 = Internal loopback
The transmitter output (L1TXD) is internally connected to the receiver input
(L1RXD). The receiver and the transmitter operate normally. Transmitted data ap-
pears on the L1TXD pin, and any external data received on L1RXD pin is ignored.
In this mode, L1RQ is asserted normally, and L1GR is ignored.
11 = Loopback control
In this mode, the transmitter output (TXD1/L1TXD) is internally connected to the
receiver input (RXD1/L1RXD). The TXD1/L1TXD, TXD2, TXD3, RTS1, RTS2,
and RTS3 pins will be high, but L1TXD will be three-stated in IDL and PCM
modes. This mode may be used to accomplish multiplex mode loopback testing
without affecting the multiplexed layer 1 interface. It also prevents an SCC's indi-
vidual loopback (configured in the SCM) from affecting the pins of its associated
NMSI interface.
15
14
13
12
11
10
9
8
SETZ
SYNC/SCIT
SDIAG1
SDIAG0
SDC2
SDC1
B2RB
B2RA
7
6
5
4
3
2
1
0
B1RB
B1RA
DRB
DRA
MSC3
MSC2
MS1
MS0