
Communications Processor (CP)
MOTOROLA
MC68302 USER’S MANUAL
4-109
Bits 11, 9–8—Reserved for future use.
V.110—V.110 Mode
0 = DDCMP mode; synchronous DDCMP is chosen.
1 = V.110 mode; the V.110 protocol description is in 4.5.15 V.110 Controller.
SYNF—Transmit SYN1–SYN2 or IDLE between Messages and Control the RTS Pin
0 = Send ones between messages. RTS is negated between messages.
NOTE
The DDCMP controller can transmit ones in both NRZ and NRZI data encoded formats. The
minimum number of ones transmitted is 17.
1 = Send SYN1–SYN2 pairs between messages. RTS is always asserted. Note that
SYN1 and SYN2 may be the same character.
ENC—Data Encoding Format
0 = Nonreturn to Zero (NRZ). A one is a high level; a zero is a low level.
1 = Nonreturn to Zero Inverted (NRZI). A one is represented by no change in the level;
a zero is represented by a change in the level. The receiver decodes NRZI, but a
clock must be supplied. The transmitter encodes NRZI.
COMMON SCC MODE BITS—See 4.5.3 SCC Mode Register (SCM) for a description of the
DIAG1, DIAG0, ENR, ENT, MODE1, and MODE0 bits.
4.5.14.10 DDCMP Receive Buffer Descriptor (Rx BD)
The CP reports information about the received data for each buffer using the BDs. The Rx
BD is shown in Figure 4-36. The CP closes the current buffer, generates a maskable inter-
rupt, and starts to receive data in the next buffer after any of the following events:
Receiving the received message length number of bytes (RMLG)
Detecting an error
Detecting a full receive buffer
Issuing the ENTER HUNT MODE command
Figure 4-36. DDCMP Receive Buffer Descriptor
The first word of the Rx BD contains control and status bits. Bits 15–12 are written by the
user before the buffer is linked to the Rx BD table, and bits 5–0 and 11–8 are set by the IMP
15
E
14
X
13
W
12
I
11
L
10
H
9
8
7
—
6
—
5
4
3
2
1
0
OFFSET + 0
OFFSET + 2
OFFSET + 4
T2
T1
CF
FR
PR
CR
OV
CD
DATA LENGTH
OFFSET +6
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)