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參數(shù)資料
| 型號(hào)： | MCM64E918 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8M Bit synchronous late write fast static RAM(8M位同步遲寫(xiě)快速靜態(tài)RAM) |
| 中文描述： | 晚8分位同步靜態(tài)隨機(jī)存儲(chǔ)器寫(xiě)入速度（800萬(wàn)位同步遲寫(xiě)快速靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 10/24頁(yè) |
| 文件大?。?/td> | 503K |
| 代理商： | MCM64E918 |
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MCM64E918
MCM64E836
10
MOTOROLA FAST SRAM
DEVICE
UNDER
TEST
ZQ
50
50
0.75 V
0.75 V
Vref
250
Figure 1. Test Loads
50
50
0.75 V
0.75 V
50
50
5 pF
5 pF
16.7
DQ
16.7
16.7
0.75 V
(a) Test Load
(b) Test Load
AC INPUT CHARACTERISTICS
(See Notes 1 through 3)
Parameter
Symbol
Min
Max
Notes
AC Input Logic High (See Figure 2)
VIH (ac)
VIL (ac)
Vref (ac)
Vdif (ac)
Vref + 200 mV
—
—
AC Input Logic Low (See Figure 3)
Vref – 200 mV
5% Vref (dc)
VDDQ + 600 mV
Input Reference Peak–to–Peak AC Voltage
—
4
Clock Input Differential Voltage
400 mV
NOTES:
1. Inputs may undershoot to VSS – 1 V (peak) for up to 35% tKHKH or 1.0 ns, whichever is smaller, and VSS – 1.5 V instantaneous peak
undershoot.
2. Inputs may overshoot to 3.3 V for up to 35% tKHKH or 1.0 ns, whichever is smaller, and 3.6 V instantaneous peak overshoot.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo-
nent superimposed on Vref may not exceed 5% of the dc component of Vref.
CROSSING POINT
VDDQ
VSS
VTR
VDIF
VCP
VCM*
Figure 2. Differential Inputs/Common Mode Input Voltage
* VCM, the Common Mode Input Voltage, equals VTR – [(VTR – VCP)/2].
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