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參數資料
型號: MCM64E918
廠商: Motorola, Inc.
英文描述: 8M Bit synchronous late write fast static RAM(8M位同步遲寫快速靜態RAM)
中文描述: 晚8分位同步靜態隨機存儲器寫入速度(800萬位同步遲寫快速靜態內存)
文件頁數: 9/24頁
文件大小: 503K
代理商: MCM64E918
MCM64E918
MCM64E836
9
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(2.375 V
VDD
2.625 V, 1.4 V
VDDQ
1.9 V, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0.25 V to 1.25 V
1 V/ns (20% to 80%)
. . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
VDDQ/2
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . .
R
θ
JA Device
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDDQ/2
. . . . . . . . . . .
Differential Cross–Point
TBD
READ AND WRITE CYCLE TIMING
Parameter
Symbol
b l
64E918–3.0
64E836–3.0
64E918–3.3
64E836–3.3
64E918–4.0
64E836–4.0
64E918–4.4
64E836–4.4
64E918–5.0
64E836–5.0
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tKHKH
tKHKL
3
3.3
4
4.4
5
ns
CK Clock High Pulse
Width
1.2
1.3
1.6
1.8
2
ns
CK Clock Low Pulse
Width
tKLKH
1.2
1.3
1.6
1.8
2
ns
CQ Low to CQ High
tCLCH
tKLKH
– 100
ps
tKLKH
+ 100
ps
tKLKH
– 100
ps
tKLKH
+ 100
ps
tKLKH
– 100
ps
tKLKH
+ 100
ps
tKLKH
– 100
ps
tKLKH
+ 100
ps
tKLKH
– 100
ps
tKLKH
+ 100
ps
CQ High to CQ Low
tCHCL
tKHKL
– 100
ps
tKHKL
+ 100
ps
tKHKL
– 100
ps
tKHKL
+ 100
ps
tKHKL
– 100
ps
tKHKL
+ 100
ps
tKHKL
– 100
ps
tKHKL
+ 100
ps
tKHKL
– 100
ps
tKHKL
+ 100
ps
Setup Times:
Address Valid to CK
Crossing
Burst Control Valid to
CK Crossing
Data In Valid to CK
Crossing
tAVKH
tBVKH
tDVKX
0.5
0.5
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.5
0.5
0.3
ns
1
Hold Times:
CK Crossing to
Address Don’t Care
CK Crossing to Burst
Control Don’t Care
CK Crossing to Data
In Don’t Care
tKHAX
tKHBX
tKXDX
0.5
0.5
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.5
0.5
0.3
ns
1
CK Crossing to CQ High
tKXCH
tKXCL
tCHQV
tCLQV
tCHQX
tCLQX
tKHQX1
tCHQZ
0.7
1.5
0.7
1.65
0.7
2
0.7
2.2
0.7
2.5
ns
CK Crossing to CQ Low
0.7
1.5
0.7
1.65
0.7
2
0.7
2.2
0.7
2.5
ns
CQ High to Output Valid
0.20
0.20
0.20
0.20
0.20
ns
1
CQ Low to Output Valid
0.20
0.20
0.20
0.20
0.20
ns
1
CQ High to Output Hold
– 0.20
– 0.20
– 0.20
– 0.20
– 0.20
ns
1, 2
CQ Low to Output Hold
– 0.20
– 0.20
– 0.20
– 0.20
– 0.20
ns
1, 2
CK High to Output Low–Z
0.5
0.5
0.5
0.5
0.5
ns
2, 3
CQ High to Output
High–Z
– 0.20
0.25
– 0.20
0.3
– 0.20
0.35
– 0.20
0.35
– 0.20
0.35
ns
2, 4
NOTES:
1. Guaranteed by design and characterization.
2. This parameter sampled and not 100% tested.
3. Measured at
±
200 mV from steady state.
4. Measured at
±
200 mV from steady state. See Figure 1b.
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