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參數資料
| 型號： | MCM64E918 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8M Bit synchronous late write fast static RAM(8M位同步遲寫快速靜態RAM) |
| 中文描述： | 晚8分位同步靜態隨機存儲器寫入速度（800萬位同步遲寫快速靜態內存） |
| 文件頁數： | 5/24頁 |
| 文件大小： | 503K |
| 代理商： | MCM64E918 |
MCM64E918
MCM64E836
5
MOTOROLA FAST SRAM
BUS CYCLE STATE DIAGRAM
READ SINGLE
WRITE SINGLE
READ DOUBLE
WRITE DOUBLE
ADVANCE ADDRESS
BY ONE
(SEE NOTE 1)
LOAD NEW
ADDRESS
DESELECT
SUPPLY
VOLTAGE
PROVIDED
B1
NOTE:
1. Advance internal address in accordance with burst order with wrap–around. Burst–length of four.
ADVANCE ADDRESS
BY ONE
(SEE NOTE 1)
ADVANCE ADDRESS
BY TWO
(SEE NOTE 1)
ADVANCE ADDRESS
BY TWO
(SEE NOTE 1)
POWER UP
B1
B2, B3
B1
B2, B3
B2, B3
B1
B2, B3
B1
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1
THREE–WIRE SYNCHRONOUS FUNCTION CONTROLS
(See Notes 1 through 4)
B1
B2
B3
Function Launched at Next Clock
D
Q (n)
Q (n + 1)
0
0
1
Write Single, Load New Address
Next Edge
High–Z
High–Z
0
0
0
Write Double, Load New Address
Both Edges
High–Z
High–Z
0
1
1
Read Single, Load New Address
High–Z
Next CQ + Edge
Next CQ + Edge
0
1
0
Read Double, Load New Address
High–Z
Both CQ Edges
Both CQ Edges
1
1
X
Increment Address, Continue Previous Function
X
X
X
1
0
X
Deselect, Pipeline High–Z
X
X
High–Z
NOTES:
1. X = don’t care.
2. Deselect usage is discussed in the Functional Description section.
3. Outputs will be in high–Z during power up, except CQ and CQ.
4. Double reads and writes occur per burst sequence.
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