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參數資料
| 型號： | MPC9350 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低壓PLL時鐘驅動器 |
| 文件頁數： | 6/12頁 |
| 文件大小： | 282K |
| 代理商： | MPC9350 |
MPC9350
MOTOROLA
TIMING SOLUTIONS
APPLICATIONS INFORMATION
Programming the MPC9350
The MPC9350 clock driver outputs can be configured into
several divider modes, in addition the internal feedback of the
device allows for flexibility in establishing two input to output
frequency relationships. The output division settings establish
the output frequency relationship. The output divider of the
four output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
“Output Frequency Relationship FBSEL = 1, (VC0 = 32 * CLK)”
and “Output Frequency Relationship FBSEL = 0, (VC0 = 16 *
CLK)” illustrate the various output configurations. The tables
describes the outputs using the input clock frequency CLK as
a reference.
In addition, it must be ensured that the VCO will be stable
given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while
the VCO frequency range is specified from 200 MHz to 400
MHz and should not be exceeded for stable operation.
Output Frequency Relationshipa FBSEL = 1, (VC0 = 32 * CLK)
Inputs
Outputs
FSELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 datasheet more input to output
relationships in external feedback mode.
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QA
QB
QC0, QC1
8 * CLK
8 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
QD0-QD4
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
a.
Output Frequency Relationshipa FBSEL = 0, (VC0 = 16 * CLK)
Inputs
Outputs
FSELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351datasheet for more input to output
relationships in external feedback mode.
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QA
QB
QC0, QC1
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
QD0-QD4
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
a.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC9350AC | 功能描述:時鐘驅動器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9350ACR2 | 功能描述:時鐘發生器及支持產品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:時鐘驅動器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9350FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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