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參數(shù)資料
| 型號： | N643GT5KI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 64兆位（4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 25/49頁 |
| 文件大小： | 382K |
| 代理商： | N643GT5KI |
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May 8, 2006 25692A2
Am29BDS643G
23
D A T A S H E E T
Figure 1.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7 or DQ6/DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a
hardware reset
immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
The host system may also initiate the chip erase
command sequence while the device is in the unlock
bypass mode. The command sequence is two cycles
cycles in length instead of six cycles. See Table 10 for
details on the unlock bypass command sequences.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 14 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the
address and data requirements for the sector erase
command sequence.
The device does
not
require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of no less than 50 μs occurs. During the
time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector
erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sec-
tors. The time between these additional cycles must be
less than 50 μs, otherwise erasure may begin. Any
sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written.
Any command other than
Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode.
The
system must rewrite the command sequence and any
additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Table 10 for program command sequence.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| N643GT7GI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| N643GT7MI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| N6455A | 制造商:Agilent Technologies 功能描述:HARD COPY MANUAL, 4000X-SERIES OSCILLOSCOPE; Plug Type:-; Accessory Type:Hard Copy Manual; For Use With:InfiniiVision 4000 X-Series Oscilloscopes ;RoHS Compliant: NA |
| N6456A | 制造商:AGILENT TECHNOLOGIES, INC. 功能描述:Rackmount Kit for 2000 and 3000X Series Oscilloscopes 制造商:Agilent Technologies 功能描述:Bulk 制造商:Agilent Technologies 功能描述:OPTION RACK MOUNT KIT FOR X-SERIES 制造商:Agilent Technologies 功能描述:RACK MOUNT KIT; Accessory Type:Rackmount Kit; For Use With:Agilent InfiniiVision 2000X / 3000X Series Oscilloscopes ;RoHS Compliant: NA 制造商:Agilent Technologies 功能描述:Rack mount kit |
| N6457A | 制造商:AGILENT TECHNOLOGIES, INC. 功能描述:Soft Carrying Case and Front Panel Cover for 2000 and 3000X Series Scopes 制造商:Agilent Technologies 功能描述:Bulk 制造商:Agilent Technologies 功能描述:ACCESSORY SOFT CASE AND FRONT PANEL 制造商:Agilent Technologies 功能描述:ACCESSORY, SOFT CASE AND FRONT PANEL 制造商:Agilent Technologies 功能描述:SOFT CARRYING CASE AND FRONT PANEL COVER; Accessory Type:Case and Front Panel Cover; For Use With:Agilent InfiniiVision 2000X / 3000X Series Oscilloscopes ;RoHS Compliant: NA 制造商:Agilent Technologies 功能描述:Soft Carrying Case |
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