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| 型號： | N643GT5KI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 64兆位（4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發模式閃存 |
| 文件頁數： | 5/49頁 |
| 文件大小： | 382K |
| 代理商： | N643GT5KI |
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May 8, 2006 25692A2
Am29BDS643G
3
D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of
Simultaneous Operation Circuit. . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6
Special Handling Instructions for FBGA Package ....................6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations .......................................................9
Requirements for Asynchronous ReadOperation(Non-Burst) 9
Requirements for Synchronous (Burst) ReadOperation ..........9
Continuous Burst ......................................................................9
8-, 16-, and 32-Word Linear Burst with Wrap Around ............10
Table 2. Burst Address Groups .......................................................10
Programmable Wait State ......................................................10
Handshaking Feature .............................................................10
Power Saving Function ...........................................................11
Simultaneous Read/Write Operations with ZeroLatency .......11
Writing Commands/Command Sequences ............................11
Accelerated Program Operation .............................................11
Autoselect Functions ..............................................................11
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Input .............................................12
Output Disable Mode ..............................................................12
Hardware Data Protection ......................................................12
Low VCC Write Inhibit ............................................................12
Write Pulse “Glitch” Protection ...............................................12
Logical Inhibit ..........................................................................12
Common Flash Memory Interface (CFI). . . . . . . 13
Table 3. CFI Query Identification String ..........................................13
Table 4. System Interface String .....................................................14
Table 5. Device Geometry Definition ..............................................14
Table 6. Primary Vendor-Specific Extended Query ........................15
Table 7. Sector Address Table ........................................................16
Command Definitions . . . . . . . . . . . . . . . . . . . . . .20
Reading Array Data ................................................................20
Set Configuration Register Command Sequence ...................20
Table 8. Burst Modes ......................................................................20
Handshaking Feature .............................................................20
Table 9. Wait States for Handshaking .............................................21
Enable PS (Power Saving) Mode CommandSequence ........21
Sector Lock/Unlock Command Sequence ..............................21
Reset Command .....................................................................21
Autoselect Command Sequence ............................................21
Program Command Sequence ...............................................22
Unlock Bypass Command Sequence .....................................22
Figure 1. Program Operation.......................................................... 23
Chip Erase Command Sequence ...........................................23
Sector Erase Command Sequence ........................................23
Erase Suspend/Erase Resume Commands ...........................24
Figure 2. Erase Operation.............................................................. 24
Table 10. Command Definitions ....................................................25
Write Operation Status . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling .................................................................26
Figure 3. Data# Polling Algorithm.................................................. 26
DQ6: Toggle Bit I ....................................................................27
Figure 4. Toggle Bit Algorithm........................................................ 27
DQ2: Toggle Bit II ...................................................................28
Table 11. DQ6 and DQ2 Indications ..............................................28
Reading Toggle Bits DQ6/DQ2 ...............................................28
DQ5: Exceeded Timing Limits ................................................28
DQ3: Sector Erase Timer .......................................................29
Table 12. Write Operation Status ...................................................29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 5. Maximum Negative OvershootWaveform...................... 30
Figure 6. Maximum Positive OvershootWaveform........................ 30
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. Test Setup....................................................................... 32
Table 13. Test Specifications .........................................................32
Key to Switching Waveforms. . . . . . . . . . . . . . . . 32
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Input Waveforms and
Measurement Levels...................................................................... 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Synchronous/Burst Read ........................................................33
Figure 9. Burst Mode Read (66 and 54 MHz)................................ 33
Figure 10. Burst Mode Read (40 MHz).......................................... 34
Asynchronous Read ...............................................................35
Figure 11. Asynchronous Mode Read............................................ 35
Figure 12. Reset Timings............................................................... 36
Erase/Program Operations .....................................................37
Figure 13. Program Operation Timings.......................................... 38
Figure 14. Chip/Sector Erase Operations...................................... 39
Figure 15. Accelerated Unlock Bypass ProgrammingTiming........ 40
Figure 16. Data# Polling Timings (DuringEmbeddedAlgorithm).. 41
Figure 17. Toggle Bit Timings (DuringEmbeddedAlgorithm)........ 41
Figure 18. 8-, 16-, and 32-Word Linear Burst
Address Wrap Around.................................................................... 42
Figure 19. Latency with Boundary Crossing (54MHzand66MHz) 42
Figure 20. Initial Access with Power Saving (PS)
FunctionandAddressBoundaryLatency...................................... 43
Figure 21. Example of Extended Valid Address Reducing Wait State
Usage............................................................................................. 43
Figure 22. Back-to-Back Read/Write Cycle Timings...................... 44
Erase and Programming Performance . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 46
VDA044—44-Ball Very Thin Fine-Pitch Ball Grid Array
(FBGA)9.2 x8.0mmPackage ...............................................46
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
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