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參數(shù)資料
型號： S29CL032J0RFFI110
廠商： SPANSION LLC
元件分類： PROM
英文描述： 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80
文件頁數(shù)： 15/78頁
文件大小： 1825K
代理商： S29CL032J0RFFI110
20
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
8 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command register (see Table 8.1). The command register itself does not
occupy any addressable memory location; rather, it is composed of latches that store the com-
mands, along with the address and data information needed to execute the command. The
contents of the register serve as input to the internal state machine; the state machine outputs
dictate the function of the device. Writing incorrect address and data values or writing them in
an improper sequence may place the device in an unknown state, in which case the system must
write the reset command in order to return the device to the reading array data mode.
8.1
Device Operation Table
The device must be set up appropriately for each operation. Table 8.1 describes the required
state of each control pin for any particular operation.
Legend: L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care.
Notes:
1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB
Table 8.1 Device Bus Operation
Operation
CE# OE# WE# RESET#
CLK
ADV#
Addresses
Data
(DQ0–DQ31)
Read
LL
H
X
AIN
DOUT
Asynchronous Write
LH
L
H
X
AIN
DIN
Synchronous Write
LH
L
H
AIN
DIN
Standby (CE#)
HX
X
H
X
HIGH Z
Output Disable
L
H
X
HIGH Z
Reset
XX
X
L
X
HIGH Z
PPB Protection Status (Note 2)
LL
H
X
Sector Address,
A9 = VID,
A7 – A0 = 02h
00000001h, (protected)
A6 = H
00000000h (unprotect)
A6 = L
Burst Read Operations
Load Starting Burst Address
LX
H
AIN
X
Advance Burst to next address
with appropriate Data presented
on the Data bus
L
H
X
Burst Data Out
Terminate Current Burst
Read Cycle
HX
H
XX
HIGH Z
Terminate Current Burst
Read Cycle with RESET#
XX
H
L
X
HIGH Z
Terminate Current Burst
Read Cycle;
Start New Burst Read Cycle
LH
H
AIN
X
相關(guān)PDF資料
PDF描述
S29CL032J0RFFN130 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80
S29CL032J1JFAI110 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL032J1MFAN120 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL032J0PQAN102 1M X 32 FLASH 3.3V PROM, 54 ns, PQFP80
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