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參數資料
| 型號： | S29CL032J0RFFI110 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數： | 19/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFFI110 |
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S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
8.4.1
2-, 4-, 8- Double Word Linear Burst Operation
In a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from
consecutive addresses that are determined by the group within which the starting address falls.
Note that 1 double word = 32 bits. See Table 8.2 for all valid burst output sequences.
The IND/WAIT# signal, or End of Burst Indicator signal, transitions active (VIL) during the last
transfer of data in a linear burst read before a wrap around. This transition indicates that the
system should initiate another ADV# to start the next burst access. If the system continues to
clock the device, the next access wraps around to the starting address of the previous burst ac-
cess. The IND/WAIT# signal is floating when not active.
The IND/WAIT# signal is controlled by the OE# signal. If OE# is at VIH, the IND/WAIT# signal
floats and is not driven. If OE# is at VIL, the IND/ WAIT# signal is driven at VIH until it transitions
to VIL, indicating the end of the burst sequence. Table 8.3 lists the valid combinations of the Con-
figuration Register bits that impact the IND/WAIT# timing. See Figure 8.3 for the IND/WAIT#
timing diagram.
Notes:
1. The default configuration in the Control Register for Bit 6 is "1," indicating that the device delivers data on the rising edge
of the CLK signal.
2. The device is capable of holding data for one CLK cycle.
3. If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults
back to asynchronous read mode. When this happens, the DQ data bus signal floats and the Configuration Register
contents are reset to their default conditions.
4. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to VIH at any time during
the burst linear or burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal.
5. Restarting a burst cycle is accomplished by taking CE# and ADV# to VIL.
6. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the
previous address is discarded and subsequent burst transfers are invalid. A new burst is initiated when ADV# transitions
back to VIH before a clock edge.
7. The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin
to VIH during a burst operation floats the data bus, but the device continues to operate internally as if the burst sequence
continues until the linear burst is complete. The OE# pin does not halt the burst sequence, The DQ bus remains in the
float state until OE# is taken to VIL.
8. Halting the burst sequence is accomplished by either taking CE# to VIH or re-issuing a new ADV# pulse.
Table 8.2 32- Bit Linear and Burst Data Order
Data Transfer Sequence (Independent of the WORD# pin)
Output Data Sequence (Initial Access Address)
(x16)
Two Linear Data Transfers
0-1 (A0 = 0)
1-0 (A0 = 1)
Four Linear Data Transfers
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
Eight Linear Data Transfers
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
Table 8.3 Valid Configuration Register Bit Definition for IND/WAIT#
CR9
(DOC)
CR8
(WC)
CR6
(CC)
Definition
00
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
01
1
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising
CLK edge
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