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參數資料
| 型號： | TFP9431CPAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-64 |
| 文件頁數： | 17/18頁 |
| 文件大小： | 241K |
| 代理商： | TFP9431CPAP |
TFP9431
PanelBus
DVI RECEIVER WITH TRIPLE DAC
SLDS122A – MARCH 2000 – REVISED JUNE 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VID(2)
Differential input sensitivity
150
1560
mVp-p
tps
Analog input intra-pair (+ to -) differential skew
0.4
tbit
tccs
Analog Input inter-pair or channel-to-channel skew
1
tpix§
tijit
Worse case differential input clock jitter tolerance
TBD
ns
tf1
Fall time of data and control signals#, ||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
2.9
3.1
ns
tr1
Rise time of data and control signals#, ||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
2.84
3.2
ns
tr2
Rise time of ODCK clock#
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
tf2
Fall time of ODCK clock#
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
tsu1
Setup time, data and control signal to falling edge of ODCK
(OCK_INV = low)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
th1
Hold time, data and control signal to falling edge of ODCK
(OCK_INV = low)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
tsu2
Setup time, data and control signal to rising edge of ODCK
(OCK_INV = high)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
th2
Hold time, data and control signal to rising edge of ODCK
(OCK_INV = high)||
ST = Low,
CL=5 pF
ST = High,
CL=10 pF
TBD
ns
fODCK
ODCK frequency
25
165
MHz
ODCK duty-cycle
40%
50%
60%
tpd(PDL)
Propagation delay time from PD low to Hi-Z outputs
9
ns
tpd(PDOL)
Propagation delay time from PDO low to Hi-Z outputs
9
ns
tp(PDH-V)
Delay time from PD rising edge to inputs active
ns
twL(PD-MIN)
Pulse duration, minimum time PD low
ns
tt(HSC)
Transition time between DE transition to SCDT lowk
1e6
tpix
tt(FSC)
Transition time between DE transition to SCDT highk
1600
tpix
ts
Settling time, analog output (see Note 5)
5
ns
tr3
Rise time, analog output (see Note 6)
2
ns
Analog output skew
0
2
ns
Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
tbit is 1/10 the pixel time, tpix
§ tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in
2-pixel/clock mode.
Measured differentially at 50% crossing using ODCK output clock as trigger.
# Rise and fall times measured as time between 20% and 80% of signal amplitude.
|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]
kLink active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
NOTES:
5. Measured within +–1 LSB from 50% point of full-scale transition to output settling (settling time does not include clock and data
feedthrough.
6. Measured between 10% and 90% of full-scale transition.
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