
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
19
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
15 bit RGB 4:4:4
CLKIN is equal to 1x pixel clock. This format is only supported in VESA mode and can be used for PC graphics
applications that do not require full 8-bit resolution on each color component.
Clock generator (CGEN) / Clock driver (CDRV)
The clock generator/clock driver blocks generate all on-chip clocks for 4:2:2 to 4:4:4 and 2x video oversampling.
The DMAN setting controls whether the input data is 4:2:2 or 4:4:4 sampled, and whether a 30, 20 or 10 bit
interface is used. This selection affects the clock input frequency assumed to be present on CLKIN:
-
30 bit 4:4:4 : 1x pixel clock. 4:2:2 to 4:4:4 interpolation should be bypassed. Optional 2x oversampling available
for formats with pixel clock up to 80MHz.
-
20 bit 4:2:2 : 1x pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available for formats with
pixel clock up to 150MHz. Optional 2x oversampling available for formats with pixel clock up to 80MHz.
-
10 bit 4:2:2 (ITU) : 1/2x pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available for
formats with pixel clock up to 150MHz. Optional 2x oversampling available for formats with pixel clock up to
80MHz.