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參數資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數： | 7/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
15
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Detailed Functional Description
Data manager (DMAN)
Supported input formats
INPUT INTERFACE
TIMING CONTROL
SYNCHRONIZATION
30 bit
20 bit
10
bit
2
16
bit
15
bit
Embedded
timing
Dedicated
timing
Master
Slave
[PRESET]
HDTV
–
SMPTE296M
progressive (720P)
X
(4:4:4)
X
(4:2:2)
X
[PRESET]
HDTV
–
SMPTE274M
progressive (1080P)
X
(4:4:4)
X
(4:2:2)
X
[PRESET]
HDTV
–
SMPTE274M
interlaced (1080I)
X
(4:4:4)
X
(4:2:2)
X
[GENERIC]
HDTV
X
(4:4:4)
X
(4:2:2)
X
[PRESET]
SDTV-ITU.1358 (525P)
X
3
X
[PRESET]
SDTV
–
ITU-R.BT470
(525I)
X
4
X
[PRESET]
SDTV-ITU-R.BT470
(625I )
X
5
X
[GENERIC]
SDTV
X
(4:4:4)
X
(4:2:2)
X
[PRESET]
VESA
X
6
X
7
X
8
X
2 The ITU-R.BT656 output bus on THS8200 can be enabled via an I2C register bit when the device is configured to
receive data over a 10bit input interface, to send this data to an external device. In other DMAN modes, this output
should remain off (register ‘data_tristate656’)
3 SMPTE293M-compliant
4 ITU.R-BT656 compliant
5 ITU-R.BT656 compliant
6 since PC graphics data is normally only 8 bit wide, only 3x8 bit (8MSB’s of each bus) will be used. Color space
converter bypass required for modes with pixelclock > 150MSPS.
7 see footnote for 30-bit VESA format
8 see footnote for 30-bit VESA format
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