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參數資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數： | 25/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
31
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Internal Synchronization
The pixel and line counters of the DTG are reset by internal signals. In slave mode (THS8200 slaves to external
video input source) these signals are derived from either the embedded SAV/EAV codes or the dedicated
Hsync/Vsync/FID inputs. In master mode, these counters are in free-run and HS_IN/VS_IN/FID signals are now
generated by THS8200 based on the programmed field/frame parameters. Master mode is only available in VESA
mode for the DTG.
The user can delay, in both horizontal and vertical directions, the 0-reference of the DTG by programming the input
delay registers. Physically the horizontal and vertical DTG startup values are altered. The effect is that, when a
vertical or horizontal sync is received, either from dedicated inputs or from embedded SAV/EAV codes, the output
frame starts at position (x,y). This ensures that e.g. the output video frame can be centered on the display.
Based on the 0-reference of the DTG, the linetypes are generated and the DIGMUX will select between the video
input and the DTG output for each linetype. All horizontal timings of the different linetypes are programmable,
including the portion of the video line seen as active video. A complete overview of all available linetypes in either
SDTV or HDTV mode will be presented later.
Additionally Hsync/Vsync outputs can be generated, synchronized to the THS8200 DAC outputs. These outputs
are programmable in width, position and polarity, based on the horizontal/vertical pixel counters, and thus
independently of the DTG reference. This ensures that independent synchronization is possible between the
composite sync output inserted into the DAC output(s) and the dedicated Hsync/Vsync outputs. Because of their
programmability, these output signals could be used for other purposes as well, e.g. Vsync could be programmed
as a signal active during the VBI.
The figure below shows how the internal pixel & line counters are synchronized to internal HS and VS signals in
slave mode. HS & VS are internal signals derived from either HS_IN,VS_IN or from embedded SAV/EAV codes in
the input video data. Since the 0 reference of the DTG is determined by these counters, the ‘dtg2_vs_in_dly’ and
‘dtg2_hs_in_dly’ register settings influence both HS_OUT, VS_OUT and composite sync output timing. The
‘dtg2_vdly<1,2>’ and ‘dtg2_hdly’ settings on the other hand only affect HS_OUT,VS_OUT since they are
downstream of the pixel counter. Likewise, ‘dtg2_hlength’ and ‘dtg2_vlength<1,2>’ only affect these dedicated sync
output signals.
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