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參數資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數： | 72/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
8
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Clock generator (CGEN)
The clock generator is an analog DLL (delay-locked loop) - based circuit and provides a 2x clock from the CLKIN
input. The 2x clock is used by the CDRV block for 2x video interpolation. Some video formats also require a rate
clock e.g. used for 4:2:2 to 4:4:4 conversion.
Clock driver (CDRV)
The Clock DRiVe block generates all on-chip clocks. Its inputs are control signals from the digital logic, the original
CLKIN, and the 2X clock from CGEN. Outputs include a half rate clock, full rate clock, and a 2x full rate clock. The
clocks are used for both optional on-chip interpolation processes: 4:2:2 to 4:4:4 interpolation & 1x to 2x video
oversampling.
I2C Host Interface (I2CSLAVE)
The I2C interface controls and programs the internal I2C registers. The THS8200/10 I2C interface implementation
supports the ‘fast I2C’ specification (SCL: 400kHz) and allows the writing and reading of registers. An auto-
increment addressing feature simplifies block register programming. A clock input on CLKIN needs to be present in
order for the I2C interface to work.
Test block (TST)
The TeST block controls all the test functions of the THS8200. Next to manufacturing test modes, this block
contains several user test modes including a DAC internal ‘ramp’ generator and a 75% SMPTE video color bar
generator.
D/A converters (DAC)
THS8200/10 contains three DACs operating at up to 205MSPS and with an internal resolution of 11-bit. Each DAC
contains an integrated video sync inserter. The sync(s) is (are) inserted by means of additional current source
circuits on either only the green/luma (Y) channel or on all DAC output channels, in order to be compliant with both
consumer (EIA, sync-on-G/Y) as well as professional (SMPTE, sync-on-all) standards.
The DAC speed supports all ATSC formats, including 1080P, as well as all PC graphics (VESA) formats up to
UXGA@75Hz (202.5MSPS).
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