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參數資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數： | 49/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
53
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
amplitude of a logic ‘1’ bit, as prescribed by EIA-805. The CSM does not affect the amplitude of the CGMS data
insertion.
CGMS is inserted on line41 as prescribed by EIA 770 standards for progressive format display of SDTV. 14 bits
can be inserted on this line, consisting of 6 bits header and 8 bits payload. The user can directly program these bits
into the corresponding THS8200/10 registers. Care should be taken to format this data according to CGMS
semantics; the user is referred to the original standards to determine header/payload data programming. To avoid
the transmission of invalid data, the data transmitted will only be updated when the CGMS register with the highest
sub-address is programmed with ‘cgms_en’ active.
CGMS insertion is possible in either 1x or 2x interpolated video modes of THS8200/10. While EIA-805 allows the
inserted data to change on every frame, and also allows data packets that would span multiple lines (and therefore
also multiple frames, since only 1 line/frame is used for insertion), ths8200 does not support multi-line data
insertion since since it is not required for CGMS.
I2C Interface
The THS8200/10 contains a slave-only I2C interface on which both write and read are supported. The register map
shows which registers support ‘read/write’ (‘R/W’) and which are ‘read-only’ (‘R’). The device supports NORMAL
and FAST I2C modes (SCL up to 400kHz). The I2C interface is only operational when an input clock within the
allowable frequency range is received on CLKIN.
To discriminate between write and read operations, the device is addressed at separate device addresses. There
is an automatic internal sub-address increment counter to efficiently write/read multiple bytes in the register map
during one write/read operation. Furthermore, bit1 of the I2C device address is dependent upon the setting of the
I2CA pin, as follows:
If address selecting pin I2CA = ‘0’, then
WRITE address is 40hex (01000000)
READ address is 41hex (01000001)
If address selecting pin I2CA = ‘1’, then
WRITE address is 42hex (01000010)
READ address is 43hex (01000011)
WRITE FORMAT:
S
Slave address(w)
A
Sub-address
A
Data0
A
……
DataN-1
A
P
S
Start condition
Slave address(w)
0100000 (0x40) if I2CA=0 / 01000010 (0x42) if I2CA=1
A
Acknowledge, it is generated by THS8200/10
Sub-address
Sub-address of the 1
st register to write, length: 1 byte
Data0
First byte of the data
DataN-1
Nth byte of the data
P
Stop condition
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