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參數資料
| 型號： | TLV320ADC3001IYZHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁數： | 7/81頁 |
| 文件大?。?/td> | 836K |
| 代理商： | TLV320ADC3001IYZHT |
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DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
8-bit Register Data
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
DA(6)
DA(0)
RA(7)
RA(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
SDA
SCL
DA(6)
DA(0)
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
D(7)
D(0)
8-bit Register Data
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
After the master issues a START condition, it sends a byte that indicates the slave device with which it is to
communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it is to read from or write to the
slave device.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW
to acknowledge this to the slave. It then sends a clock pulse to clock the bit.
A not-acknowledge is performed by leaving SDA HIGH during an acknowledge cycle. If a device is not present
on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at
that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320ADC3001 also responds to and acknowledges a general call, which consists of the master issuing a
command with a slave address byte of 00h.
Figure 12. I2C Write
Figure 13. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental
register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmits for the
next eight clocks the data of the next incremental register.
DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between the host processor and the TLV320ADC3001 via the digital-audio serial-data
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options,
support for I2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation,
flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices
within a system directly.
Copyright
2008–2011, Texas Instruments Incorporated
15
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