
1
0
1
HPF
15
1
N
N z
H
(z)
2
D z
-
+
=
-
1
0
1
LPF
15
1
N
N z
H
(z)
2
D z
-
+
=
-
www.ti.com
SLAS659 – NOVEMBER 2009
The VOL/MICDET pin connection and functionality are shown in
Figure 1-1.As shown in
Table 5-13, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB,
and mute. However, if less maximum gain is required, then a smaller range of voltage should be applied
to the VOL/MICDET pin. This can be done by increasing the value of R2 relative to the value of (P1 + R1),
so that more voltage is available at the bottom of P1. The circuit should also be designed such that for the
values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed
AVDD/2 (see
Figure 5-1). The recommended values for R1, R2, and P1 for several maximum gains are
shown in
Table 5-14. Note that In typical applications, R1 should not be 0
, as the VOL/MICDET pin
should not exceed AVDD/2 for proper ADC operation.
Table 5-14. VOL/MICDET Pin Gain Scaling
ADC VOLTAGE
R1
P1
R2
DIGITAL GAIN RANGE
for AVDD = 3.3 V
(k
)
(k
)
(k
)
(dB)
(V)
25
0
0 V to 1.65 V
18 dB to –63 dB
33
25
7.68
0.386 V to 1.642 V
3 dB to –63 dB
34.8
25
9.76
0.463 V to 1.649 V
0 dB to –63 dB
5.6.4
Dynamic Range Compression
Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal
power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC
channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal
periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome
this problem, DRC in the TLV320DAC3120 continuously monitors the output of the DAC digital volume
control to detect its power level relative to 0 dBFS. When the power level is low, DRC increases the input
signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously
reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the ear as well as
sounding louder during nominal periods.
The DRC functionality in the TLV320DAC3120 is implemented by a combination of processing blocks in
DRC can be disabled by writing to page 0 / register 68, bits D6–D5.
DRC typically works on the filtered version of the input signal. The input signals have no audio information
at dc and extremely low frequencies; however, they can significantly influence the energy estimation
function in DRC. Also, most of the information about signal energy is concentrated in the low-frequency
region of the input signal.
To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the
DRC low-pass filter. These filters are implemented as first-order IIR filters given by
(3)
(4)
The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
29