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| 型號： | TLV320DAC3120IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 50/110頁 |
| 文件大小： | 1230K |
| 代理商： | TLV320DAC3120IRHBT |
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SLAS659 – NOVEMBER 2009
www.ti.com
Table 5-22. PLL Example Configurations
PLL_CLKIN (MHz)
PLLP
PLLR
PLLJ
PLLD
MDAC
NDAC
DOSR
fS = 44.1 kHz
2.8224
1
3
10
0
3
5
128
5.6448
1
3
5
0
3
5
128
12
1
7
560
3
5
128
13
1
6
3504
6
3
104
16
1
5
2920
3
5
128
19.2
1
4
4100
3
5
128
48
4
1
7
560
3
5
128
fS = 48 kHz
2.048
1
3
14
0
7
2
128
3.072
1
4
7
0
7
2
128
4.096
1
3
7
0
7
2
128
6.144
1
2
7
0
7
2
128
8.192
1
4
3
0
4
128
12
1
7
1680
7
2
128
16
1
5
3760
7
2
128
19.2
1
4
4800
7
2
128
48
4
1
7
1680
7
2
128
5.8
Digital Audio and Control Interface
5.8.1
Digital Audio Interface
Audio data is transferred between the host processor and the TLV320DAC3120 via the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified
data options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
NOTE
The TLV320AIC3102 has a mono DAC, which inputs the mono data from the digital audio
data serial interface as the left channel, the right channel, or a mix of the left and right
channels as (L + R) ÷ 2 (page 0 / register 63, bits D5–D4). See Figure 1-1 for the signal
flow of the DAC blocks.
The audio bus of the TLV320DAC3120 can be configured for left- or right-justified, I2S, DSP, or TDM
modes of operation, where communication with standard telephony PCM interfaces is supported within the
TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be
independently configured in either master or slave mode for flexible connectivity to a wide variety of
processors. The word clock is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see Figure 5-16). The number of bit-clock pulses in a frame may need adjustment
to accommodate various word lengths as well as to support the case when multiple TLV320DAC3120s
may share the same audio bus.
44
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3120
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| TLV320DAC3120IRHBT | 制造商:Texas Instruments 功能描述:D/A Converter (D-A) IC 制造商:Texas Instruments 功能描述:IC, DAC, 32BIT, 192KSPS, QFN-32 |
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| TLV320DAC3202CYZJR | 功能描述:音頻放大器 Low Pwr Hi Fidelity I2S Input Headset IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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