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參數資料
| 型號： | TLV320DAC3120IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數： | 60/110頁 |
| 文件大小： | 1230K |
| 代理商： | TLV320DAC3120IRHBT |
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www.ti.com
SLAS659 – NOVEMBER 2009
6
REGISTER MAP
6.1
TLV320DAC3120 Register Map
All features on this device are addressed using the I2C bus. All of the writable registers can be read back.
However, some registers contain status information or data, and are available for reading only.
The TLV320DAC3120 contains several pages of 8-bit registers, and each page can contain up to 128
registers. The register pages are divided up based on functional blocks for this device. Page 0 is the
default home page after RESET. Page control is done by writing a new page value into register 0 of the
current page.
The control registers for the TLV320DAC3120 are described in detail as follows. All registers are 8 bits in
width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant
bit.
Pages 0, 1, 3, 8–11, 12–15, and 64–95 are available for use; however, all other pages and registers are
reserved. Do not read from or write to reserved pages and registers. Also, do not write other than the
reset values for the reserved bits and read-only bits of non-reserved registers; otherwise, device
functionality failure can occur.
Table 6-1. Summary of Register Map
Page Number
Description
0
Page 0 is the default page on power up. Configuration for serial interface, digital I/O, clocking, DAC settings, etc.
1
Configuration for analog DAC, output drivers, volume controls, etc.
Register 16 controls the MCLK divider that controls the interrupt pulse duration, debounce timing, and detection block
3
clock.
8–11
DAC buffer-A filter and DRC coefficients, miniDSP general-purpose buffer-A coefficients
12–15
DAC buffer-B filter and DRC coefficients, miniDSP general-purpose buffer B-coefficients
64–95
DAC instuction RAM locations
6.2
Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial
Interfaces, Flags, Interrupts, and GPIOs
Page 0 / Register 0: Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
Page 0 / Register 1: Software Reset
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D1
R/W
0000 000
Reserved. Write only zeros to these bits.
D0
R/W
0
0: Don't care
1: Self-clearing software reset for control register
Page 0 / Register 2: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R
XXXX XXXX
Reserved. Do not write to this register.
Copyright 2009, Texas Instruments Incorporated
REGISTER MAP
53
Product Folder Link(s): TLV320DAC3120
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| TLV320DAC3202CYZJR | 功能描述:音頻放大器 Low Pwr Hi Fidelity I2S Input Headset IC RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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