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| 型號(hào)： | TLV320DAC3120IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁(yè)數(shù)： | 81/110頁(yè) |
| 文件大小： | 1230K |
| 代理商： | TLV320DAC3120IRHBT |
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SLAS659 – NOVEMBER 2009
www.ti.com
Table 6-5. Page 3 / Register 16: MCLK Divider for Programmable Delay Timer
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
1
0: Internal oscillator is used for programmable delay timer.
1: External MCLK(1) is used for programmable delay timer.
D6–D0
R/W
000 0000
MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer
000 0000: MCLK divider = 128
000 0001: MCLK divider = 1
000 0010: MCLK divider = 2
...
111 1110: MCLK divider = 126
111 1111: MCLK divider = 127
(1)
External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This
feature is provided in case a more accurate delay is desired since the internal oscillator frequency varies from device to device.
6.5
Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
Default values shown for this page only become valid 100
μs following a hardware or software reset.
Page 8 / Register 0: Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
The remaining page-8 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320DAC3120. Reserved registers should not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient
are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When
programming any coefficient value for a filter, the MSB register should always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers should be written in this sequence. Table 6-6 is a list of the page-8 registers, excepting the
previously described register 0.
Page 8 / Register 1: DAC Coefficient RAM Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Reserved. Write only the reset value.
D3
R
0
DAC miniDSP generated flag for toggling MSB of coefficient RAM address (only used in non-adaptive
mode)
D2
R/W
0
DAC Adaptive Filtering Control
0: Adaptive filtering disabled in DAC miniDSP
1: Adaptive filtering enabled in DAC miniDSP
D1
R
0
DAC Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, DAC miniDSP accesses DAC coefficient Buffer A and the external control
interface accesses DAC coefficient Buffer B
1: In adaptive filter mode, DAC miniDSP accesses DAC coefficient Buffer B and the external control
interface accesses DAC coefficient Buffer A
D0
R/W
0
DAC Adaptive Filter Buffer Switch Control
0: DAC coefficient buffers are not switched at the next frame boundary.
1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled.
This bit self-clears on switching.
72
REGISTER MAP
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3120
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| TLV320DAC3120IRHBT | 制造商:Texas Instruments 功能描述:D/A Converter (D-A) IC 制造商:Texas Instruments 功能描述:IC, DAC, 32BIT, 192KSPS, QFN-32 |
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| TLV320DAC3202CYZJR | 功能描述:音頻放大器 Low Pwr Hi Fidelity I2S Input Headset IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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