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參數資料
| 型號： | TLV320DAC32IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 16/69頁 |
| 文件大小： | 1242K |
| 代理商： | TLV320DAC32IRHBT |
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DIGITAL AUDIO DATA SERIAL INTERFACE
RIGHT JUSTIFIED MODE
BCLK
WCLK
SDIN
1
0
1
0
1/fs
LSB
MSB
LeftChannel
RightChannel
2
n1
n3
n2
n1
n3
n2
LEFT JUSTIFIED MODE
www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Audio data is transferred between the host processor and the TLV320DAC32 via the digital audio data serial
interface, or “audio bus”. The audio bus of the TLV320DAC32 can be configured for left or right justified, I2S,
DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported
within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In
addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave
mode, for flexible connectivity to a wide variety of processors.
The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or
a square-wave signal. The frequency of this clock corresponds to the maximum DAC sampling frequency
selected.
The bit clock (BCLK) is used to clock in the digital audio data across the serial bus. When in master mode, this
signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous
transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in
general the number of bit clocks per frame will be two times the data width. For example, if data width is chosen
as 16-bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode will be used by a
PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used. These cases
result in a low jitter bit clock signal being generated, having frequencies of 32*Fs or 64*Fs. In the cases of 20-bit
and 24-bit data width in master mode, the bit clocks generated in each frame will not all be of equal period, due
to the device not having a clean 40*Fs or 48*Fs clock signal readily available. The average frequency of the bit
clock signal is still accurate in these cases (being 40*Fs or 48*Fs), but the resulting clock signal has higher jitter
than in the 16-bit and 32-bit cases and may reduce the overall DAC performance.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. By
using this capability with the ability to program at what bit clock in a frame the audio data will begin, time-division
multiplexing (TDM) can be accomplished, resulting in multiple DACS able to use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a tri-state output condition.
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 26. Right Justified Serial Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Copyright 2006–2008, Texas Instruments Incorporated
23
Product Folder Link(s): TLV320DAC32
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