- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98255 > TLV320DAC32IRHBT (TEXAS INSTRUMENTS INC) SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 PDF資料下載
參數(shù)資料
| 型號： | TLV320DAC32IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 33/69頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | TLV320DAC32IRHBT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Page 0 / Register 4:
PLL Programming Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
000001
PLL J Value
000000: Reserved, do not write this sequence
000001: J = 1
000010: J = 2
000011: J = 3
…
111110: J = 62
111111: J = 63
D1–D0
R/W
00
Reserved, write only zeros to these bits
Table 1. Page 0 / Register 5:
PLL Programming Register C(1)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00000000
PLL D(13:6) – Eight most significant bits of a 14-bit unsigned integer valid values for D are from
zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be
written into these registers that would result in a D value outside the valid range.
(1)
When programming PLL D value, register 5 should always be written first, immediately followed by register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Page 0 / Register 6:
PLL Programming Register D
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
00000000
PLL D(5:0) – Six least significant bits of a 14-bit unsigned integer valid values for D are from
zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be
written into these registers that would result in a D value outside the valid range.
D1-D0
R
00
Reserved. Do not write to these bits.
Page 0 / Register 7:
DAC Datapath Setup Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Fsref setting
0: Fsref = 48-kHz
1: Fsref = 44.1-kHz
D6
R/W
0
Reserved. Only write zero to this bit.
D5
R/W
0
DAC Dual Rate Control 0: DAC dual rate mode is disabled 1: DAC dual rate mode is enabled
D4–D3
R/W
00
Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D2–D1
R/W
00
Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
D0
R/W
0
Reserved. Only write zero to this register.
Copyright 2006–2008, Texas Instruments Incorporated
39
Product Folder Link(s): TLV320DAC32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV320DAC32IRHBRG4 | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| TLV431AIDBV | 1-OUTPUT TWO TERM VOLTAGE REFERENCE, 1.24 V, PDSO5 |
| TLV431ALPRE | 1-OUTPUT TWO TERM VOLTAGE REFERENCE, PBCY3 |
| TLV431ALP | 1-OUTPUT TWO TERM VOLTAGE REFERENCE, PBCY3 |
| TLV431ALPRF | 1-OUTPUT TWO TERM VOLTAGE REFERENCE, PBCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320DAC32IRHBTG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Low Power Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC33NIZQC | 制造商:Texas Instruments 功能描述: |
| TLV320DAC33NIZQCR | 制造商:Texas Instruments 功能描述: |
| TLV320VD30 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VDSL CODEC |
| TLV320VD30PN | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。