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參數資料
型號： TMX320C6413ZTS500
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 112/140頁
文件大小： 1958K
代理商： TMX320C6413ZTS500
Reset Timing
112
April 2004
Revised May 2005
SPRS247E
7.7
Reset Timing
Table 7
17. Timing Requirements for Reset (see Figure 7
22)
NO.
400
500
UNIT
MIN
250
MAX
1
16
17
t
w(RST)
t
su(boot)
t
h(boot)
Width of the RESET pulse
Setup time, boot configuration bits valid before RESET high
Hold time, boot configuration bits valid after RESET high
μ
s
ns
ns
4E or 4C
4P
§
AEA[22:19], LENDIAN, BOOTMODE[1:0], and AECLKIN_SEL[1:0] are the boot configuration pins during device reset.
E = 1/ECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.
Select the MIN parameter value, whichever value is larger.
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The device must be reset after the oscillator has stabilized. If RESETz is low during power-up, it can be kept low until the oscillator has stabilized.
Note: a device reset does not affect the state of the oscillator.
Table 7
18. Switching Characteristics Over Recommended Operating Conditions During Reset
§#
(see Figure 7
22)
NO.
PARAMETER
400,
500
MIN
2E
2E
2E
UNIT
MAX
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
d(RSTL-ECKI)
t
d(RSTH-ECKI)
t
d(RSTL-ECKO1HZ)
t
d(RSTH-ECKO1V)
t
d(RSTL-EMIFZHZ)
t
d(RSTH-EMIFZV)
t
d(RSTL-EMIFHIV)
t
d(RSTH-EMIFHV)
t
d(RSTL-EMIFLIV)
t
d(RSTH-EMIFLV)
t
d(RSTL-HIGHIV)
t
d(RSTH-HIGHV)
t
d(RSTL-ZHZ)
t
d(RSTH-ZV)
Delay time, RESET low to ECLKIN synchronized internally
Delay time, RESET high to ECLKIN synchronized internally
Delay time, RESET low to ECLKOUT1 high impedance
Delay time, RESET high to ECLKOUT1 valid
Delay time, RESET low to EMIF Z high impedance
Delay time, RESET high to EMIF Z valid
Delay time, RESET low to EMIF high group invalid
Delay time, RESET high to EMIF high group valid
Delay time, RESET low to EMIF low group invalid
Delay time, RESET high to EMIF low group valid
Delay time, RESET low to high group invalid
Delay time, RESET high to high group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
3P + 20E
8P + 20E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8P + 20E
3P + 4E
8P + 20E
2E
16E
2E
8P + 20E
2E
8P + 20E
0
11P
0
2P
8P
18
t
d(OSCSTART)
Delay time, Internal oscillator startup time
||
CLKINSEL = 0
41032 x
OSCIN
ns
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The device must be reset after the oscillator has stabilized. If RESETz is low during power-up, it can be kept low until the oscillator has stabilized.
Note: a device reset does not affect the state of the oscillator.
#
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
||
Assuming core power supply has stabilized at recommended operating conditions.
EMIF Z group consists of:
AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, APDT., and AECLKOUT1
EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of:
ABUSREQ; AHOLDA (when the corresponding HOLD input is low)
High group consists of:
HRDY (when HPI is enabled, otherwise in Z group)
Z group consists of:
CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKS0, CLKS1, DR0, DR1, CLKR0, CLKR1, FSR0, FSR1,
TOUT0/HPI_EN, TOUT1/LENDIAN, GP0[7:0], HD[7:0], HD[15:8]/GP0[15:8], HD[21:16]/AXR1[5:0],
HD22/AFSX1, HD23/AFSR1, HD24/ACLKX1, HD25/ACLKR1, HD26/AHCLKR1, HD27/AHCLKX1,
HD28/AMUTE1, HD29/AMUTEIN1, HD30, HD31, HRDY, HDS2, HDS1/ACLKR1[3], HCS/ACLKR1[2],
HAS/ACLKR1[1], HR/W/AFSR1[3], HHWIL/AFSR1[2] (16-bit HPI mode only), HCNTL0/AFSR1[1], HCNTL1,
HINT,, ACLKR0, AFSR0, AHCLKR0, AMUTEIN0, AMUTE0, AXR0[5:0], SDA1, SCL1, SDA0, SCL0,
TDO, and EMU[11:0]
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