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參數資料
型號： TMX320C6413ZTS500
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 130/140頁
文件大小： 1958K
代理商： TMX320C6413ZTS500
Multichannel Buffered Serial Port (McBSP) Timing
130
April 2004
Revised May 2005
SPRS247E
Table 7
33. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1
(see Figure 7
40)
NO.
400
500
UNIT
MASTER
MIN
12
4
SLAVE
MIN
2
12P
5 + 24P
MAX
MAX
4
5
t
su(DRV-CKXH)
t
h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7
34. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
(see Figure 7
40)
NO.
PARAMETER
400
500
UNIT
MASTER
§
MIN
T
2
H
2
2
SLAVE
MIN
MAX
T + 3
H + 3
MAX
1
2
3
t
h(CKXH-FXL)
t
d(FXL-CKXL)
t
d(CKXL-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
#
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX high
ns
ns
ns
4
12P + 2.8
20P + 17
6
t
dis(CKXH-DXHZ)
H
2
H + 3
ns
7
t
dis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
4P + 3
12P + 17
ns
8
t
d(FXL-DXV)
Delay time, FSX low to DX valid
8P + 2
16P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§
S =
Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
8
7
6
2
1
CLKX
FSX
DX
DR
Figure 7
40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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