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參數資料
| 型號： | TMX320C6413ZTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 44/140頁 |
| 文件大小： | 1958K |
| 代理商： | TMX320C6413ZTS500 |
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Device Configurations
44
April 2004
Revised May 2005
SPRS247E
3
Device Configurations
On the C6413/C6410 device, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are software-configurable
via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
3.1
Device Configuration at Device Reset
Table 3
1 describes the C6413/C6410 device configuration pins. The logic level of the AEA[22:19],
TOUT1/LENDIAN, TOUT0/HPI_EN, and HD5 pins is latched at reset to determine the device configuration.
The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by
using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The
CLKINSEL and OSC_DIS configuration pins should remain driven to the correct levels during device operation
and must only be changed when RESET is low. The device configuration pins are sampled during reset and
are driven after the reset is removed. At this time, the control device should ensure it has stopped driving the
device configuration pins of the DSP to again avoid contention.
Table 3
1. C6413/C6410 Device Configuration Pins (
TOUT1/
LENDIAN, AEA[22:19],
TOUT0/
HPI_EN,
HD5, CLKINSEL, and OSC_DIS)
CONFIGURATION
PIN
NO.
IPD/IPU
FUNCTIONAL DESCRIPTION
TOUT1/
LENDIAN
AA1
IPU
Device Endian mode (LEND)
0
–
System operates in Big Endian mode
1
System operates in Little Endian mode (default)
AEA[22:21]
[M21,
N21]
IPD
Bootmode [1:0]
00 –
01
10
11
No boot (default mode)
HPI boot (based on HPI_EN pin)
Reserved
EMIFA 8-bit ROM boot
AEA[20:19]
[P22,
N22]
IPD
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 –
AECLKIN (default mode)
01
CPU/4 Clock Rate
10
CPU/6 Clock Rate
11
Reserved
HPI, McASP1, GP0[15:8] select
Selects whether the HPI peripheral or McASP1 peripheral, and GP0[15:8] pins are
functionally enabled
0
–
HPI is enabled and the McASP1 peripheral and GP0 [15:8] pins are disabled
(default mode);
[HPI32, if HD5 = 1; HPI16 if HD5 = 0]
1
HPI I is disabled and the McASP1 peripheral and GP0 [15:8] pins are enabled
For more detail on the peripherals (McASP1 and GP0[15:8] pins) muxed with HPI, see the
Table 3
2.
HPI peripheral bus width (HPI_WIDTH) select
0
HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used for HPI and the remaining
HD[31:16] muxed
pins function as McASP1 peripheral pins or are reserved pins in the Hi-Z state.)
1
HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
For more detail on the peripherals (McASP1 and GP0[15:8] pins) muxed with HPI, see the
Table 3
2.
TOUT0/
HPI_EN
AA2
IPD
HD5
Y13
IPU
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