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參數資料
| 型號： | TMX320C6413ZTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 49/140頁 |
| 文件大小： | 1958K |
| 代理商： | TMX320C6413ZTS500 |
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Device Configurations
49
April 2004
Revised May 2005
SPRS247E
Read Accesses
31
1
0
Reserved
LOCKSTAT
R-0
R-1
Write Accesses
31
0
LOCK
W-0
Legend:
R = Read only; R/W = Read/Write; -n = value after reset
Figure 3
3. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018]
Read/Write Accesses
Table 3
4. PCFGLOCK Register Selection Bit Descriptions
Read Accesses
BIT
31:1
NAME
Reserved
DESCRIPTION
Reserved. Read-only, writes have no effect.
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0
=
Unlocked, read accesses to the PERCFG register allowed.
1
=
Locked, write accesses to the PERCFG register do
not
modify the register state [default].
Reads are unaffected by Lock Status.
0
LOCKSTAT
Table 3
5. PCFGLOCK Register Selection Bit Descriptions
Write Accesses
BIT
NAME
DESCRIPTION
31:0
LOCK
Lock bits.
0x10C0010C = Unlocks PERCFG register accesses.
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user
must
ensure that no accesses are performed to a
peripheral while it is disabled.
In addition to the normal usage, the PCFGLOCK register can be used to override the power saver settings
specified in the PERCFG register. When the power saver feature is disabled (PCFGLOCK written with
0xC0100C01), all peripherals controlled by PERCFG are enabled. If the power saver is returned to normal
operation (PCFGLOCK written with 0x0C01C010), then the peripherals return to the operating condition
specified by PERCFG. Turning off the power saver settings will add a worst-case 50 mW of power to the overall
DSP power consumption.
Note: overriding the settings of the PERCFG register will not cause a conflict on the multiplexed pins. For
example, with the HPI and McASP1 peripherals, the HPI will still have control over the multiplexed pins
provided the TOUT0/HPI_EN pin was “0” at reset.
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