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參數資料
| 型號： | TMX320C6413ZTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 45/140頁 |
| 文件大?。?/td> | 1958K |
| 代理商： | TMX320C6413ZTS500 |
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Device Configurations
45
April 2004
Revised May 2005
SPRS247E
Table 3
1. C6413/C6410 Device Configuration Pins (
TOUT1/
LENDIAN, AEA[22:19],
TOUT0/
HPI_EN,
HD5, CLKINSEL, and OSC_DIS) (Continued)
FUNCTIONAL DESCRIPTION
IPD/IPU
NO.
CONFIGURATION
PIN
CLKINSEL
A11
IPU
PLL input clock source select
Selects whether the PLL input clock is CLKIN [pin high] or directly from the crystal oscillator
(OSCIN and OSCOUT) [pin low]. For proper device operation, this pin
must
be used in
conjunction with the OSC_DIS pin.
0
Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator)
For proper device operation, OSC_DIS
must
be 0
1
CLKIN square wave (default)
For proper device operation, OSC_DIS
must
be 1
This pin
must
be pulled to the correct level even after reset.
OSC_DIS
B7
IPU
Oscillator disable
Selects whether the Oscillator is enabled or disabled. For proper device operation, this pin
must
follow the CLKINSEL pin operation.
0
OSC enabled
1
OSC disabled (default)
This pin
must
be pulled to the correct level even after reset.
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
3.2
Peripheral Configuration at Device Reset
Some C6413/C6410 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI,
general-purpose input/output 0 pins GP0[15:8], and McASP1).
HPI, McASP1, and GP0 peripherals
The TOUT0/
HPI_EN
(AA2 pin) is latched at reset. This pin selects whether the HPI peripheral or McASP1
peripheral, and GP0[15:8] pins are functionally enabled (see Table 3
2).
Table 3
2.
TOUT0/
HPI_EN and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins)
PERIPHERAL SELECTION
PERIPHERALS SELECTED
HPI_EN
(AA2)
HD5
[HPI_WIDTH]
(Y13)
HPI
McASP1
GP0 [15:8]
DESCRIPTION
0
0
16-bit HPI
Available
N/A
HPI_EN = 0, HD5 =
0
HPI16 is enabled and McASP1 peripheral is enabled
and GP0 [15:8] pins are disabled. All multiplexed
HPI/McASP1 pins function as McASP1 pins. All
multiplexed HPI/GP0 are reserved pins in the Hi-Z state.
0
1
32-bit HPI
N/A
N/A
HPI_EN = 0, HD5 =
1
HPI32 is enabled and McASP1 peripheral and GP0
[15:8] pins are disabled. All multiplexed HPI/McASP1
and HPI/GP0 pins function as HPI pins.
HPI_EN =
1, HD5 = x (don’t care
)
HPI is disabled and the McASP1 peripheral and GP0
[15:8] pins are enabled. All multiplexed HPI/McASP1
and HPI/GP0 pins function as McASP1 and GP0 pins,
respectively. To use the GP0 pins, the appropriate bits
in the GP0EN and GP0DIR registers need to be set. All
standalone HPI pins are reserved pins in the Hi-Z state
1
x
N/A
Available
Available
The TOUT0/HPI_EN pin has an internal pulldown that enables the HPI by default. The TOUT0/HPI_EN pin
can
disable the HPI via an external
pullup resistor or be driven high during reset. The TOUT0/HPI_EN pin is
not
software-controllable.
N/A = Not available
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