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參數資料
型號: TMX320C6413ZTS500
廠商: Texas Instruments, Inc.
元件分類: 數字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數字信號處理器
文件頁數: 119/140頁
文件大小: 1958K
代理商: TMX320C6413ZTS500
Inter-Integrated Circuits (I2C) Timing
119
April 2004
Revised May 2005
SPRS247E
Table 7
23. Switching Characteristics for I2C Timings
(see Figure 7
27)
400
500
NO.
PARAMETER
STANDARD
MODE
FAST
MODE
UNIT
MIN
MAX
MIN
2.5
0.6
MAX
16
17
t
c(SCL)
t
d(SCLH-SDAL)
Cycle time, SCL
Delay time, SCL high to SDA low (for a repeated START condition)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
10
4.7
μ
s
μ
s
18
t
d(SDAL-SCLL)
4
0.6
μ
s
19
20
21
22
23
24
25
26
27
28
29
t
w(SCLL)
t
w(SCLH)
t
d(SDAV-SDLH)
t
v(SDLL-SDAV)
t
w(SDAH)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
d(SCLH-SDAH)
C
p
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I
2
C bus
devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
4.7
1.3
0.6
100
μ
s
μ
s
ns
μ
s
μ
s
ns
ns
ns
ns
μ
s
pF
4
250
0
0
0.9
4.7
1.3
1000
1000
300
300
20 + 0.1C
b
20 + 0.1C
b
20 + 0.1C
b
20 + 0.1C
b
300
300
300
300
4
0.6
10
10
25
23
19
18
22
27
20
21
17
18
28
Stop
Start
Repeated
Start
Stop
SDA
SCL
16
26
24
Figure 7
27. I2C Transmit Timings
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