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參數(shù)資料
型號: TPS65040ZQER
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71
封裝: 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71
文件頁數(shù): 12/73頁
文件大小: 1928K
代理商: TPS65040ZQER
www.ti.com
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TPS65040 OUTPUT(1) AND OPERATIONAL RANGE
PIN NAME
PIN NO.
TYPE
VOUT (V)
IOUTMAX (mA)
VOUT
A8, B8
Buck boost DC/DC converter
0.8~4.2
550
V11_V28TX
G1
Normal mode (high PSRR LDO)
2.85
130(2)
PA_VDD
F2
Switch output of V11_V28TX
2.85
20
V12_V28RX
E1
Low power mode/normal mode (high PSRR LDO)
2.85
95(3)
V_LNA_FEM
E2
Switch output of V12_V28RX
2.85
30
V13_V28A
D1
Low power mode/normal mode (high PSRR LDO)
2.85
50
V15_V18A
C2
Low power mode/normal mode (high PSRR LDO)
1.85
15
VGGE1_V28
H9
Low power mode/normal mode (high PSRR LDO)
2.85
150
VGGE2_V28
G9
Low power mode/normal mode (high PSRR LDO)
2.85
150
VGGE3_V28
F9
Low power mode/normal mode (high PSRR LDO)
2.85
100
VTCXO
J2
Normal mode (high PSRR LDO)
2.85
20
PAVREF1
A3
8-bit DAC output
0.95~2.9
5
PAVREF2
A2
8-bit DAC output
0.95~2.9
5
PAVREF3
B1
8-bit DAC output
0.95~2.9
5
AFC
J3
12-bit DAC output
0.25~2.45
0.025
SIN_SYSCLK1
J5
Clock distribution with –3 dB gain
SIN_SYSCLK2
J6
Clock distribution with –1 dB gain
SIN_SYSCLK3
J7
Clock distribution with –1 dB gain
(1)
All outputs can be controlled by serial interface, except VTCXO, PAVREF1, PAVREF2 and PAVREF3.
(2)
When the PA_VDD has load current, the maximum load current of V11_V28TX is decreased from 130 mA by the value of IOUT of
PA_VDD.
(3)
When the V_LNA_FEM has load current, the maximum load current of V12_V28RX is decreased from 95 mA by the value of IOUT of
V_LNA_FEM.
2
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